{"id":451911,"date":"2024-10-20T09:21:15","date_gmt":"2024-10-20T09:21:15","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-iec-62548-12023-tc\/"},"modified":"2024-10-26T17:25:26","modified_gmt":"2024-10-26T17:25:26","slug":"bs-iec-62548-12023-tc","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-iec-62548-12023-tc\/","title":{"rendered":"BS IEC 62548-1:2023 – TC"},"content":{"rendered":"
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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137<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
139<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
143<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
145<\/td>\n | 1 Scope 2 Normative references <\/td>\n<\/tr>\n | ||||||
148<\/td>\n | 3 Terms, definitions, symbols and abbreviated terms 3.1 Terms and definitions <\/td>\n<\/tr>\n | ||||||
154<\/td>\n | 3.2 Symbols <\/td>\n<\/tr>\n | ||||||
157<\/td>\n | 3.3 Abbreviated terms 4 Compliance with IEC 60364 series <\/td>\n<\/tr>\n | ||||||
158<\/td>\n | 5 PV array system configuration 5.1 General 5.1.1 Functional configuration of a PV system 5.1.2 PV system topologies Figures Figure 1 \u2013 General functional configuration of a PV powered system <\/td>\n<\/tr>\n | ||||||
159<\/td>\n | 5.1.3 Array electrical diagrams <\/td>\n<\/tr>\n | ||||||
160<\/td>\n | Figure 2 \u2013 PV array diagram \u2013 single string example <\/td>\n<\/tr>\n | ||||||
161<\/td>\n | Figure 3 \u2013 PV array diagram \u2013 multiple parallel string example <\/td>\n<\/tr>\n | ||||||
162<\/td>\n | Figure 4 \u2013 PV array diagram \u2013 multiple parallel string examplewith array divided into sub-arrays <\/td>\n<\/tr>\n | ||||||
163<\/td>\n | Figure 5 \u2013 PV array example using a PCE with multiple MPPT DC inputs <\/td>\n<\/tr>\n | ||||||
164<\/td>\n | Figure 6 \u2013 PV array example using a PCE with multiple DCinputs internally connected to a common DC bus <\/td>\n<\/tr>\n | ||||||
165<\/td>\n | 5.1.4 Use of PCE with multiple DC inputs 5.1.5 PV arrays using DCUs <\/td>\n<\/tr>\n | ||||||
166<\/td>\n | Figure 7 \u2013 PV string constructed using DCUs <\/td>\n<\/tr>\n | ||||||
167<\/td>\n | Figure 8 \u2013 Example of partial DCU string <\/td>\n<\/tr>\n | ||||||
168<\/td>\n | Figure 9 \u2013 PV parallel strings constructed using DCUs <\/td>\n<\/tr>\n | ||||||
169<\/td>\n | Figure 10 \u2013 PV string(s) connected to DCUs <\/td>\n<\/tr>\n | ||||||
170<\/td>\n | 5.1.6 Series-parallel configuration 5.1.7 Batteries in systems <\/td>\n<\/tr>\n | ||||||
171<\/td>\n | 5.1.8 Backfeed and reverse currents 5.1.9 Considerations due to prospective fault current conditions within a PV array 5.1.10 Considerations due to operating temperature <\/td>\n<\/tr>\n | ||||||
172<\/td>\n | 5.1.11 Performance issues <\/td>\n<\/tr>\n | ||||||
173<\/td>\n | 5.1.12 Potential induced degradation 5.1.13 Corrosion 5.1.14 Mechanical design <\/td>\n<\/tr>\n | ||||||
174<\/td>\n | 5.1.15 Mechanical loads on PV structures <\/td>\n<\/tr>\n | ||||||
176<\/td>\n | 6 Safety issues 6.1 General 6.2 Protection against electric shock 6.2.1 General 6.2.2 Protective measure: double or reinforced insulation 6.2.3 Protective measure: extra-low-voltage provided by SELV or PELV 6.3 Protection against thermal effects 6.3.1 General <\/td>\n<\/tr>\n | ||||||
177<\/td>\n | 6.3.2 Protection against fire caused by arcs 6.3.3 Protection against arc flash 6.4 Protection against the effects of insulation faults 6.4.1 General <\/td>\n<\/tr>\n | ||||||
178<\/td>\n | 6.4.2 Segregation of PV circuits from other circuits 6.4.3 Earth fault detection and indication requirements <\/td>\n<\/tr>\n | ||||||
180<\/td>\n | Tables Table 1 \u2013 Requirements for different system types basedon PCE separation and PV array functional earthing <\/td>\n<\/tr>\n | ||||||
181<\/td>\n | Table 2 \u2013 Minimum insulation resistance thresholds for detection of failure of insulation to earth <\/td>\n<\/tr>\n | ||||||
183<\/td>\n | Table 3 \u2013 Trip current of functional earthing overcurrent protection. <\/td>\n<\/tr>\n | ||||||
184<\/td>\n | 6.5 Protection against overcurrent 6.5.1 General 6.5.2 Requirement for overcurrent protection <\/td>\n<\/tr>\n | ||||||
185<\/td>\n | 6.5.3 Requirements for overcurrent protection of circuits <\/td>\n<\/tr>\n | ||||||
186<\/td>\n | Table 4 \u2013 Overcurrent protection nominal rating <\/td>\n<\/tr>\n | ||||||
187<\/td>\n | 6.5.4 Overcurrent protection for PV systems connected to batteries Figure 11 \u2013 Example of a PV array diagram where strings are groupedunder one overcurrent protection device per group <\/td>\n<\/tr>\n | ||||||
188<\/td>\n | 6.5.5 Overcurrent protection location 6.6 Protection against effects of lightning and overvoltage 6.6.1 General <\/td>\n<\/tr>\n | ||||||
189<\/td>\n | 6.6.2 Protection against overvoltage Table 5 \u2013 Calculation of the critical length Lcrit <\/td>\n<\/tr>\n | ||||||
190<\/td>\n | 7 Selection and erection of electrical equipment 7.1 General <\/td>\n<\/tr>\n | ||||||
191<\/td>\n | 7.2 Component requirements 7.2.1 General 7.2.2 Current rating of PV circuits <\/td>\n<\/tr>\n | ||||||
192<\/td>\n | 7.2.3 PV modules Table 6 \u2013 Minimum current rating of circuits <\/td>\n<\/tr>\n | ||||||
193<\/td>\n | 7.2.4 PV array and PV string combiner boxes <\/td>\n<\/tr>\n | ||||||
194<\/td>\n | 7.2.5 Fuses 7.2.6 Circuit breakers used for overcurrent protection <\/td>\n<\/tr>\n | ||||||
195<\/td>\n | 7.2.7 Isolation means and isolation means with breaking capabilities <\/td>\n<\/tr>\n | ||||||
197<\/td>\n | 7.2.8 Cables <\/td>\n<\/tr>\n | ||||||
199<\/td>\n | 7.2.9 Plugs, sockets and connectors in PV circuits Figure 12 \u2013 Examples of reinforced protection of wiring <\/td>\n<\/tr>\n | ||||||
200<\/td>\n | 7.2.10 Wiring in combiner boxes 7.2.11 Bypass diodes <\/td>\n<\/tr>\n | ||||||
201<\/td>\n | 7.2.12 Blocking diodes 7.2.13 Power conversion equipment (PCE) including DC conditioning units (DCUs) <\/td>\n<\/tr>\n | ||||||
202<\/td>\n | 7.3 Location and installation requirements 7.3.1 Isolation means Table 7 \u2013 Isolation means in PV array installations <\/td>\n<\/tr>\n | ||||||
204<\/td>\n | 7.3.2 Earthing and bonding arrangements <\/td>\n<\/tr>\n | ||||||
205<\/td>\n | Figure 13 \u2013 PV array exposed conductive partsfunctional earthing\/bonding decision tree <\/td>\n<\/tr>\n | ||||||
206<\/td>\n | Figure 14 \u2013 Exposed conductive parts earthing in a PV array <\/td>\n<\/tr>\n | ||||||
207<\/td>\n | 7.3.3 Wiring system <\/td>\n<\/tr>\n | ||||||
210<\/td>\n | Figure 15 \u2013 Examples of string wiring with minimum loop area <\/td>\n<\/tr>\n | ||||||
211<\/td>\n | 8 Acceptance 9 Operation\/maintenance 10 Marking and documentation 10.1 Equipment marking 10.2 Requirements for signs 10.3 Identification of a PV installation 10.4 Labelling of PV array and PV string combiner boxes <\/td>\n<\/tr>\n | ||||||
212<\/td>\n | 10.5 Labelling of isolation means 10.5.1 General 10.5.2 PV array isolation means with breaking capabilities 10.6 Warning sign for anti-PID equipment 10.7 Documentation <\/td>\n<\/tr>\n | ||||||
213<\/td>\n | Annex A (informative)Examples of signs Figure A.1 \u2013 Example of sign required on PV array combiner boxes (10.4) Figure A.2 \u2013 Example of switchboard sign for identification of PV on a building <\/td>\n<\/tr>\n | ||||||
214<\/td>\n | Annex B (informative)Examples of system earthingconfigurations in PV arrays Figure B.1 \u2013 Functionally earthed system topologies <\/td>\n<\/tr>\n | ||||||
215<\/td>\n | Figure B.2 \u2013 Non-earth-referenced system topologies <\/td>\n<\/tr>\n | ||||||
216<\/td>\n | Figure B.3 \u2013 Non-separated system topologies <\/td>\n<\/tr>\n | ||||||
217<\/td>\n | Annex C (informative)Blocking diode C.1 General C.2 Use of blocking diodes to prevent overcurrent\/fault current in arrays C.3 Examples of blocking diode use in fault situations C.3.1 General C.3.2 Short circuit in PV string <\/td>\n<\/tr>\n | ||||||
218<\/td>\n | Figure C.1 \u2013 Effect of blocking diode where there is a short circuit in PV string Figure C.2 \u2013 Effect of blocking diode where there is an earth faulton a system with earthing on the negative side <\/td>\n<\/tr>\n | ||||||
219<\/td>\n | C.4 Specification of blocking diode C.5 Heat dissipation design for blocking diode Figure C.3 \u2013 Effect of blocking diode where there isan earth fault on a system with positive side earthing <\/td>\n<\/tr>\n | ||||||
221<\/td>\n | Annex D (informative)Arc fault detection and interruption in PV arrays Figure D.1 \u2013 Examples of types of arcs in PV arrays <\/td>\n<\/tr>\n | ||||||
222<\/td>\n | Annex E (normative)DVC limits Table E.1 \u2013 Summary of the limits of the decisive voltage classes <\/td>\n<\/tr>\n | ||||||
223<\/td>\n | Annex F (normative)Determination of maximum voltage and maximum currents in PV circuits F.1 UOC MAX F.1.1 PV array maximum voltage <\/td>\n<\/tr>\n | ||||||
224<\/td>\n | F.1.2 PV strings constructed using DC conditioning units Table F.1 \u2013 Voltage correction factors for crystallineand multi-crystalline silicon PV modules <\/td>\n<\/tr>\n | ||||||
225<\/td>\n | F.2 String maximum current F.3 Calculation of potential fault currents originating from the array F.3.1 General F.3.2 String F.3.3 Sub-array F.3.4 Array <\/td>\n<\/tr>\n | ||||||
226<\/td>\n | F.4 KI factor \u2013 general F.5 KCorr factor \u2013 under unique environmental conditions Table F.2 \u2013 Environmental conditions covered by KCorr = 1,0 <\/td>\n<\/tr>\n | ||||||
227<\/td>\n | F.6 KCorr factor \u2013 non optimally oriented monofacial arrays F.7 KCorr factor \u2013 bifacial arrays Table F.3 \u2013 Example KCorr values at different orientations and tilt for 47\u00ba north latitude <\/td>\n<\/tr>\n | ||||||
228<\/td>\n | F.8 KCorr factor \u2013 for arrays containing non-optimally oriented bifacial modules <\/td>\n<\/tr>\n | ||||||
229<\/td>\n | Annex G (normative)Backfeed current and PV reverse currents under fault conditions G.1 General G.2 Illustrated examples Figure G.1 \u2013 Backfeed from inverter with single PV input and internal battery <\/td>\n<\/tr>\n | ||||||
230<\/td>\n | Figure G.2 \u2013 Inverter with multiple PV inputs and external battery <\/td>\n<\/tr>\n | ||||||
231<\/td>\n | G.3 Backfeed currents and PV reverse currents where subarrays are not combined in the PCE Figure G.3 \u2013 Backfeed where subarrays are combined externally to PCE <\/td>\n<\/tr>\n | ||||||
233<\/td>\n | Annex H (normative)Anti-PID H.1 General H.2 DC bias applied during night Figure H.1 \u2013 Example anti-PID control using bias on dc side at night <\/td>\n<\/tr>\n | ||||||
234<\/td>\n | H.3 DC bias applied to array output Figure H.2 \u2013 Example of anti-PID control using bias on DC side <\/td>\n<\/tr>\n | ||||||
235<\/td>\n | H.4 DC bias applied to AC system Figure H.3 \u2013 Example of anti-PID control using bias on AC side <\/td>\n<\/tr>\n | ||||||
237<\/td>\n | Annex I (informative)Arc flash <\/td>\n<\/tr>\n | ||||||
238<\/td>\n | Annex J (normative)Qualification of DCU group voltage J.1 Overview J.2 Test 1: Maximum voltage operational test procedure J.3 Test 2: Overvoltage test <\/td>\n<\/tr>\n | ||||||
240<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Tracked Changes. Photovoltaic (PV) arrays – Design requirements<\/b><\/p>\n |