BS ISO/IEC 14165-151:2017:2018 Edition
$215.11
Information technology. Fibre channel – Fibre Channel BaseT (FC-BaseT)
| Published By | Publication Date | Number of Pages |
| BSI | 2018 | 106 |
This part of ISO/IEC 14165 describes extensions to the Fibre Channel signaling and physical layer requirements defined in ISO/IEC 14165‑142, Fibre Channel – Physical Interfaces 2, to transport Fibre Channel over the commonly available 4-pair balanced copper cablings specified in ISO/IEC 11801:2002 and TIA/EIA‑568‑B.2‑2001. This standard is one of the Fibre Channel family of standards.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 2 | undefined |
| 4 | CONTENTS |
| 9 | FOREWORD |
| 11 | INTRODUCTION |
| 12 | 1 Scope 2 Normative references |
| 13 | 3 Terms, definitions, abbreviations, symbols, and conventions 3.1 Terms and definitions |
| 16 | 3.2 Editorial conventions 3.3 Abbreviations, acronyms, and symbols Tables Table 1 – ISO and American Conventions |
| 17 | 3.4 Keywords |
| 18 | 3.5 State Diagram notation 3.5.1 State Diagram conventions Figures Figure 1 – State diagram notation example |
| 19 | 3.5.2 State Diagram variables 3.5.3 State Diagram timers 3.5.4 State transitions |
| 20 | 3.5.5 Operators Table 2 – State Diagram Operators |
| 21 | 4 Structure and concepts 4.1 Overview Figure 2 – FC-BaseT topology |
| 22 | 4.2 Relationship with other standards Figure 3 – FC-BaseT relationship to the OSI Reference Model,the Fibre Channel Levels, and the IEEE 802.3 LAN Model Table 3 – FC-BaseT design goals for data rates and cable reachesfor the cabling channels specified by ISO/IEC11801:2002/AMD2:2010 |
| 23 | 4.3 FC-BaseT PHY logical model Figure 4 – An FC-BaseT PHY logical model |
| 24 | 4.4 FC-BaseT usage of XGMII Table 4 – XGMII frequencies for FC-BaseT Table 5 – XGMII characters |
| 25 | 4.5 Operation of FC-BaseT 4.5.1 Overview Table 6 – FC-BaseT symbol and data rates |
| 26 | 4.5.2 PCS overview Figure 5 – PCS and PMA functional block diagram |
| 27 | 4.5.3 PMA overview 4.6 FC-BaseT service primitives and interfaces 4.6.1 Overview 4.6.2 PMA service interface 4.6.2.1 Overview |
| 28 | 4.6.2.2 PMA_TXMODE.indication Figure 6 – PCS and PMA service interfaces |
| 29 | 4.6.2.3 PMA_CONFIG.indication 4.6.2.4 PMA_UNITDATA.request |
| 30 | 4.6.2.5 PMA_UNITDATA.indication 4.6.2.6 PMA_SCRSTATUS.request |
| 31 | 4.6.2.7 PMA_PCSSTATUS.request 4.6.2.8 PMA_RXSTATUS.indication 4.6.2.9 PMA_REMRXSTATUS.request |
| 32 | 4.6.3 Management function interface 4.6.3.1 Overview 4.6.3.2 PMA_LINK.request 4.6.3.3 PMA_LINK.indication |
| 33 | 4.7 FC-BaseT Nomenclature Figure 7 – FC-BaseT nomenclature |
| 34 | 5 Physical Coding Sublayer (PCS) 5.1 Overview 5.2 PCS reset function Figure 8 – PCS reference diagram |
| 35 | 5.3 PCS transmit function 5.3.1 Overview Figure 9 – PCS transmit bit ordering |
| 36 | 5.3.2 36/33 transcoding Table 7 – Fibre Channel words |
| 37 | Table 8 – XGMII representation of Fibre Channel words Table 9 – 36/33 transcoding Table 10 – 36/33 transcoding examples |
| 38 | 5.3.3 Error detecting code |
| 39 | 5.3.4 PCS scrambling Figure 10 – Side-stream scrambler for the Master PHY |
| 40 | Figure 11 – Side-stream scrambler for the Slave PHY |
| 41 | 5.3.5 Schläfli Lattice coding Figure 12 – 4D PAM-8 Schläfli Lattice encoder |
| 42 | 5.3.6 Trellis coding Figure 13 – 4D PAM-8 Trellis encoder Table 11 – Bit to symbols mapping |
| 43 | 5.3.7 Generation of PMA training sequences Figure 14 – Generation of PMA training PAM-2 sequences Table 12 – PMA training sequences |
| 44 | 5.4 PCS receive function 5.4.1 Overview Figure 15 – PCS receive bit ordering |
| 45 | 5.4.2 Decoding Figure 16 – 4D PAM-8 Schläfli Lattice decoder |
| 46 | 5.4.3 PCS descrambling Figure 17 – Side-stream descrambler for the Master PHY Figure 18 – Side-stream descrambler for the Slave PHY |
| 47 | 5.4.4 33/36 transcoding |
| 48 | 5.4.5 PCS synchronization 5.5 State Diagrams Table 13 – PCS synchronization state variables |
| 49 | Figure 19 – PCS synchronization state diagram |
| 50 | 6 PMA Sublayer and Medium Dependent Interface 6.1 PMA Overview Figure 20 – PMA Reference Diagram |
| 51 | 6.2 PMA Functions 6.2.1 PMA Reset function 6.2.2 PMA Transmit function 6.2.3 PMA Receive Function |
| 52 | 6.2.4 PHY Control Function |
| 53 | Table 14 – Idle2 and Idle3 Ordered Sets |
| 54 | Figure 21 – Example of Link Establishment |
| 55 | 6.2.5 Link Monitor Function 6.2.6 Clock Recovery Function 6.2.7 State Diagrams Table 15 – PHY Control and Link Monitor State Variables |
| 56 | Table 16 – PHY Control and Link Monitor Timers |
| 57 | Figure 22 – PHY Control State Diagram |
| 58 | 6.3 PMA Electrical Specification 6.3.1 Isolation and EMC Requirements 6.3.2 Test Modes 6.3.2.1 Overview Figure 23 – Link Monitor State Diagram |
| 59 | Table 17 – Management Register Settings for Test Modes |
| 60 | 6.3.2.2 Test Fixtures Figure 24 – Transmitter Test Fixture A Figure 25 – Transmitter Test Fixture B |
| 61 | 6.3.3 Transmitter Electrical Specifications 6.3.3.1 Overview 6.3.3.2 Transmitter Output Droop Figure 26 – Test Mode 1 Output (not to scale) Table 18 – Disturbing Signal Frequency Table 19 – Droop Requirements |
| 62 | 6.3.3.3 Transmitter Distortion 6.3.3.4 Transmitter Timing Jitter |
| 63 | 6.3.3.5 Transmitter Power Spectral Density (PSD) and Power Level Figure 27 – 4GFC-BaseT Transmitter PSD at 5dBm |
| 64 | Figure 28 – 2GFC-BaseT Transmitter PSD at 5dBm |
| 65 | Figure 29 – 1GFC-BaseT Transmitter PSD at 5dBm |
| 66 | 6.3.3.6 Transmitter Power Schedule 6.3.3.7 Transmit Clock Frequency 6.3.4 Receiver Electrical Specifications 6.3.4.1 Overview 6.3.4.2 Receiver Differential Input Signals Table 20 – Transmitter Power Schedule Table 21 – Transmitter Frequency Requirements |
| 67 | 6.3.4.3 Receiver Frequency Tolerance 6.3.4.4 Alien Crosstalk Noise Rejection Table 23 – Alien Noise Requirements Table 22 – Receiver Frequency Requirements |
| 68 | 6.4 MDI Specification 6.4.1 Overview 6.4.2 MDI Mechanical Specification Figure 30 – MDI Jack Connector Figure 31 – Balanced Cabling Plug Connector |
| 69 | 6.4.3 Automatic MDI/MDI-X Configuration 6.4.4 MDI Electrical Specification 6.4.5 MDI Fault tolerance 6.5 Link Segment Characteristics 6.5.1 Overview Table 24 – Assignment of PMA Signals to MDI and MDI-X Contacts Table 25 – FC-BaseT MDI Electrical Requirements |
| 70 | 6.5.2 FC-BaseT Link Topology 6.5.3 FC-BaseT Cable Plant Requirements Figure 32 – FC-BaseT Link Topology Table 26 – FC-BaseT Cable Plant Requirements |
| 71 | 7 Elasticity FIFO 7.1 Overview Figure 33 – FC-BaseT elasticity FIFO |
| 72 | 7.2 Ordered sets processing Figure 34 – Example of E-FIFO implementation Table 27 – Extended Fill Words |
| 73 | 7.3 Clock skew compensation Figure 35 – FC-BaseT clock skew compensation |
| 75 | 8 PHY startup procedure 8.1 Overview 8.2 Host speeds determination 8.3 Host synchronization |
| 76 | 8.4 FC-BaseT auto-negotiation 8.4.1 Overview |
| 77 | 8.4.2 FC-BaseT support Figure 36 – Base page encoding Table 28 – Technology Ability Field |
| 78 | 8.4.3 Master-Slave relationship Figure 37 – Unformatted page encoding Table 29 – Unformatted code field of the first unformatted page |
| 79 | 8.4.4 Cable length estimation Table 30 – Master-Slave seed assignment |
| 80 | 8.4.5 Tentative Operating Speed Determination Table 31 – Unformatted code field of the second unformatted page |
| 81 | 8.4.6 Configuration resolution Table 32 – Unformatted code field of the third unformatted page |
| 82 | 8.5 Speed downshift function 8.6 State diagrams |
| 83 | Table 33 – Cable length estimation state variables (part 1 of 3) |
| 85 | Table 34 – Cable length estimation timers |
| 86 | Figure 38 – Clock detect state diagram |
| 87 | Figure 39 – Clock loopback state diagram |
| 88 | 9 Port management 9.1 Overview 9.2 FC-BaseT management registers Table 35 – FC-BaseT registers (part 1 of 2) |
| 90 | 9.3 Control Register Table 36 – FC-BaseT control register bits (part 1 of 3) |
| 93 | 9.4 Status Register Table 37 – FC-BaseT status register bits (part 1 of 3) |
| 95 | 9.5 Speed Downshift Register Table 38 – FC-BaseT speed downshift register bits |
| 96 | 9.6 Test Register 9.7 SNR Margin Registers Table 39 – FC-BaseT test register bits Table 40 – FC-BaseT SNR margin registers bits (part 1 of 2) |
| 97 | 9.8 Auto-Negotiation Pages Registers |
| 98 | Table 41 – FC-BaseT auto-negotiation pages registers bits (part 1 of 2) |
| 100 | Annex A A.1 Overview A.2 Notation A.3 Additional mappings Table A.1 – Additional 36/33 mappings |
| 101 | Table A.2 – 6-bit encoding of XGMII control characters |
| 102 | Annex B Figure B.1 – 4D symbol error rate in function of SNR |
| 104 | Annex C Table C.1 – Recommended transmitter power schedule |
