IEEE P1149.10 D90 March2016 DRAFT
$16.25
IEEE Draft High Speed Test Access Port and On-chip Distribution Architecture
| Published By | Publication Date | Number of Pages |
| IEEE | N/A | 101 |
New IEEE Standard – Unapproved Draft. Circuitry that may be built into an integrated circuit to assist in the test, maintenance and support of assembled printed circuit boards, assembled multi-die packages and the test of die internal circuits is defined. The circuitry includes a packet decoder and standard architecture through which instructions and test data are communicated. The standard leverages the languages of IEEE Std. 1149.1 in order to describe and operate the onchip circuits.
