IEEE 1804-2017

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IEEE Standard for Fault Accounting and Coverage Reporting(FACR) for Digital Modules

Published By	Publication Date	Number of Pages
IEEE	2017	29

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Description

New IEEE Standard – Active. The standard formalizes aspects of fault models as they are relevant to the generation of test patterns for digital circuits. Its scope includes (i) fault counting, (ii) fault classification, and (iii) fault coverage reporting across different ATPG (automatic test pattern generation) tools, for the single stuck-at fault model. With this standard, it shall be incumbent on all ATPG tools (which comply with this standard) to report fault coverage in a uniform way. This will facilitate the generation of a uniform coverage (and hence a uniform test quality) metric for large chips (including systems-on-chips – SOCs) with different cores and modules, for which test patterns have been independently generated.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1804™-2017 Front cover
2	Title page
4	Important Notices and Disclaimers Concerning IEEE Standards Documents
7	Participants
8	Introduction
9	Contents
10	1. Overview 1.1 Scope 1.2 Purpose
11	1.3 Organization of this document 2. Definitions, acronyms, and abbreviations 2.1 Definitions
13	2.2 Acronyms and abbreviations 3. Fault classification and test coverage reporting 3.1 Taxonomy
15	3.2 Classification mnemonics 3.3 Metrics
16	3.4 Illustrations of standard fault classification
19	4. Fault modeling 4.1 Standard Verilog primitives 4.2 User-defined primitives (UDPs)
20	4.3 Memory models
23	4.4 Flip-flops and latches
25	4.5 Abstract models (including black-box models) 4.6 Fault accounting for IP blocks containing analog components
26	5. Fault accounting methods and rules 5.1 Fault accounting rules 5.2 Application of fault accounting standard—common cases
27	6. Summary
28	Annex A (informative) Bibliography
29	Back cover