BS EN 62680-1:2013:2014 Edition
$215.11
Universal serial bus interfaces for data and power – Universal serial bus specification, revision 2.0
| Published By | Publication Date | Number of Pages |
| BSI | 2014 | 770 |
The specification is primarily targeted to peripheral developers and system OEMs, but provides valuable information for platform operating system/ BIOS/ device driver, adapter IHVs/ISVs, and platform/adapter controller vendors. This specification can be used for developing new products and associated software.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 5 | INTRODUCTION |
| 6 | English CONTENTS |
| 18 | 1 Chapter 1 Introduction 1.1 Motivation 1.2 Objective of the Specification |
| 19 | 1.3 Scope of the Document 1.4 USB Product Compliance 1.5 Document Organization |
| 20 | 2 Chapter 2 Terms and Abbreviations |
| 26 | 3 Chapter 3 Background 3.1 Goals for the Universal Serial Bus 3.2 Taxonomy of Application Space |
| 27 | 3.3 Feature List |
| 29 | 4 Chapter 4 Architectural Overview 4.1 USB System Description 4.1.1 Bus Topology |
| 30 | 4.2 Physical Interface |
| 31 | 4.2.1 Electrical 4.2.2 Mechanical 4.3 Power |
| 32 | 4.3.1 Power Distribution 4.3.2 Power Management 4.4 Bus Protocol 4.5 Robustness |
| 33 | 4.5.1 Error Detection 4.5.2 Error Handling 4.6 System Configuration 4.6.1 Attachment of USB Devices 4.6.2 Removal of USB Devices 4.6.3 Bus Enumeration |
| 34 | 4.7 Data Flow Types 4.7.1 Control Transfers 4.7.2 Bulk Transfers 4.7.3 Interrupt Transfers 4.7.4 Isochronous Transfers |
| 35 | 4.7.5 Allocating USB Bandwidth 4.8 USB Devices 4.8.1 Device Characterizations |
| 36 | 4.8.2 Device Descriptions |
| 38 | 4.9 USB Host: Hardware and Software 4.10 Architectural Extensions |
| 39 | 5 Chapter 5 USB Data Flow Model 5.1 Implementer Viewpoints |
| 40 | 5.2 Bus Topology |
| 41 | 5.2.1 USB Host 5.2.2 USB Devices |
| 42 | 5.2.3 Physical Bus Topology |
| 43 | 5.2.4 Logical Bus Topology |
| 44 | 5.2.5 Client Software-to-function Relationship 5.3 USB Communication Flow |
| 46 | 5.3.1 Device Endpoints |
| 47 | 5.3.2 Pipes |
| 49 | 5.3.3 Frames and Microframes 5.4 Transfer Types |
| 50 | 5.4.1 Table Calculation Examples |
| 51 | 5.5 Control Transfers 5.5.1 Control Transfer Data Format |
| 52 | 5.5.2 Control Transfer Direction 5.5.3 Control Transfer Packet Size Constraints |
| 53 | 5.5.4 Control Transfer Bus Access Constraints |
| 55 | 5.5.5 Control Transfer Data Sequences |
| 56 | 5.6 Isochronous Transfers 5.6.1 Isochronous Transfer Data Format 5.6.2 Isochronous Transfer Direction 5.6.3 Isochronous Transfer Packet Size Constraints |
| 58 | 5.6.4 Isochronous Transfer Bus Access Constraints |
| 59 | 5.6.5 Isochronous Transfer Data Sequences 5.7 Interrupt Transfers 5.7.1 Interrupt Transfer Data Format 5.7.2 Interrupt Transfer Direction 5.7.3 Interrupt Transfer Packet Size Constraints |
| 60 | 5.7.4 Interrupt Transfer Bus Access Constraints |
| 63 | 5.7.5 Interrupt Transfer Data Sequences 5.8 Bulk Transfers 5.8.1 Bulk Transfer Data Format 5.8.2 Bulk Transfer Direction 5.8.3 Bulk Transfer Packet Size Constraints |
| 64 | 5.8.4 Bulk Transfer Bus Access Constraints |
| 65 | 5.8.5 Bulk Transfer Data Sequences |
| 66 | 5.9 High-Speed, High Bandwidth Endpoints 5.9.1 High Bandwidth Interrupt Endpoints |
| 67 | 5.9.2 High Bandwidth Isochronous Endpoints |
| 68 | 5.10 Split Transactions 5.11 Bus Access for Transfers |
| 69 | 5.11.1 Transfer Management |
| 71 | 5.11.2 Transaction Tracking |
| 73 | 5.11.3 Calculating Bus Transaction Times |
| 75 | 5.11.4 Calculating Buffer Sizes in Functions and Software 5.11.5 Bus Bandwidth Reclamation 5.12 Special Considerations for Isochronous Transfers |
| 76 | 5.12.1 Example Non-USB Isochronous Application |
| 78 | 5.12.2 USB Clock Model |
| 80 | 5.12.3 Clock Synchronization 5.12.4 Isochronous Devices |
| 88 | 5.12.5 Data Prebuffering |
| 89 | 5.12.6 SOF Tracking 5.12.7 Error Handling |
| 90 | 5.12.8 Buffering for Rate Matching |
| 92 | 6 Chapter 6 Mechanical 6.1 Architectural Overview 6.2 Keyed Connector Protocol |
| 93 | 6.3 Cable 6.4 Cable Assembly 6.4.1 Standard Detachable Cable Assemblies |
| 95 | 6.4.2 High-/full-speed Captive Cable Assemblies |
| 97 | 6.4.3 Low-speed Captive Cable Assemblies |
| 99 | 6.4.4 Prohibited Cable Assemblies 6.5 Connector Mechanical Configuration and Material Requirements |
| 100 | 6.5.1 USB Icon Location 6.5.2 USB Connector Termination Data |
| 101 | 6.5.3 Series “A” and Series “B” Receptacles |
| 104 | 6.5.4 Series “A” and Series “B” Plugs |
| 107 | 6.6 Cable Mechanical Configuration and Material Requirements |
| 108 | 6.6.1 Description 6.6.2 Construction |
| 111 | 6.6.3 Electrical Characteristics 6.6.4 Cable Environmental Characteristics 6.6.5 Listing 6.7 Electrical, Mechanical, and Environmental Compliance Standards |
| 117 | 6.7.1 Applicable Documents 6.8 USB Grounding 6.9 PCB Reference Drawings |
| 121 | 7 Chapter 7 Electrical 7.1 Signaling |
| 124 | 7.1.1 USB Driver Characteristics |
| 131 | 7.1.2 Data Signal Rise and Fall, Eye Patterns |
| 140 | 7.1.3 Cable Skew 7.1.4 Receiver Characteristics |
| 142 | 7.1.5 Device Speed Identification |
| 143 | 7.1.6 Input Characteristics |
| 146 | 7.1.7 Signaling Levels |
| 159 | 7.1.8 Data Encoding/Decoding 7.1.9 Bit Stuffing |
| 161 | 7.1.10 Sync Pattern 7.1.11 Data Signaling Rate 7.1.12 Frame Interval |
| 162 | 7.1.13 Data Source Signaling |
| 164 | 7.1.14 Hub Signaling Timings |
| 165 | 7.1.15 Receiver Data Jitter |
| 167 | 7.1.16 Cable Delay |
| 168 | 7.1.17 Cable Attenuation |
| 169 | 7.1.18 Bus Turn-around Time and Inter-packet Delay |
| 170 | 7.1.19 Maximum End-to-end Signal Delay |
| 171 | 7.1.20 Test Mode Support |
| 172 | 7.2 Power Distribution 7.2.1 Classes of Devices |
| 176 | 7.2.2 Voltage Drop Budget |
| 177 | 7.2.3 Power Control During Suspend/Resume |
| 178 | 7.2.4 Dynamic Attach and Detach |
| 179 | 7.3 Physical Layer 7.3.1 Regulatory Requirements 7.3.2 Bus Timing/Electrical Characteristics |
| 189 | 7.3.3 Timing Waveforms |
| 192 | 8 Chapter 8 Protocol Layer 8.1 Byte/Bit Ordering 8.2 SYNC Field 8.3 Packet Field Formats 8.3.1 Packet Identifier Field |
| 193 | 8.3.2 Address Fields |
| 194 | 8.3.3 Frame Number Field 8.3.4 Data Field |
| 195 | 8.3.5 Cyclic Redundancy Checks 8.4 Packet Formats 8.4.1 Token Packets |
| 196 | 8.4.2 Split Transaction Special Token Packets |
| 201 | 8.4.3 Start-of-Frame Packets |
| 202 | 8.4.4 Data Packets |
| 203 | 8.4.5 Handshake Packets |
| 204 | 8.4.6 Handshake Responses |
| 205 | 8.5 Transaction Packet Sequences |
| 214 | 8.5.1 NAK Limiting via Ping Flow Control |
| 218 | 8.5.2 Bulk Transactions |
| 223 | 8.5.3 Control Transfers |
| 226 | 8.5.4 Interrupt Transactions 8.5.5 Isochronous Transactions |
| 231 | 8.6 Data Toggle Synchronization and Retry |
| 232 | 8.6.1 Initialization via SETUP Token 8.6.2 Successful Data Transactions 8.6.3 Data Corrupted or Not Accepted |
| 233 | 8.6.4 Corrupted ACK Handshake |
| 234 | 8.6.5 Low-speed Transactions |
| 235 | 8.7 Error Detection and Recovery 8.7.1 Packet Error Categories 8.7.2 Bus Turn-around Timing |
| 236 | 8.7.3 False EOPs |
| 237 | 8.7.4 Babble and Loss of Activity Recovery |
| 238 | 9 Chapter 9 USB Device Framework 9.1 USB Device States 9.1.1 Visible Device States |
| 242 | 9.1.2 Bus Enumeration 9.2 Generic USB Device Operations |
| 243 | 9.2.1 Dynamic Attachment and Removal 9.2.2 Address Assignment 9.2.3 Configuration |
| 244 | 9.2.4 Data Transfer 9.2.5 Power Management 9.2.6 Request Processing |
| 246 | 9.2.7 Request Error |
| 247 | 9.3 USB Device Requests 9.3.1 bmRequestType 9.3.2 bRequest 9.3.3 wValue |
| 248 | 9.3.4 wIndex 9.3.5 wLength 9.4 Standard Device Requests |
| 250 | 9.4.1 Clear Feature |
| 251 | 9.4.2 Get Configuration 9.4.3 Get Descriptor |
| 252 | 9.4.4 Get Interface 9.4.5 Get Status |
| 254 | 9.4.6 Set Address 9.4.7 Set Configuration |
| 255 | 9.4.8 Set Descriptor 9.4.9 Set Feature |
| 256 | 9.4.10 Set Interface |
| 257 | 9.4.11 Synch Frame 9.5 Descriptors |
| 258 | 9.6 Standard USB Descriptor Definitions 9.6.1 Device |
| 260 | 9.6.2 Device_Qualifier 9.6.3 Configuration |
| 262 | 9.6.4 Other_Speed_Configuration 9.6.5 Interface |
| 264 | 9.6.6 Endpoint |
| 267 | 9.6.7 String |
| 268 | 9.7 Device Class Definitions 9.7.1 Descriptors 9.7.2 Interface(s) and Endpoint Usage |
| 269 | 9.7.3 Requests |
| 270 | 10 Chapter 10 USB Host: Hardware and Software 10.1 Overview of the USB Host 10.1.1 Overview |
| 273 | 10.1.2 Control Mechanisms 10.1.3 Data Flow |
| 274 | 10.1.4 Collecting Status and Activity Statistics 10.1.5 Electrical Interface Considerations 10.2 Host Controller Requirements 10.2.1 State Handling |
| 275 | 10.2.2 Serializer/Deserializer 10.2.3 Frame and Microframe Generation |
| 276 | 10.2.4 Data Processing 10.2.5 Protocol Engine 10.2.6 Transmission Error Handling |
| 277 | 10.2.7 Remote Wakeup 10.2.8 Root Hub 10.2.9 Host System Interface 10.3 Overview of Software Mechanisms 10.3.1 Device Configuration |
| 279 | 10.3.2 Resource Management |
| 280 | 10.3.3 Data Transfers |
| 281 | 10.3.4 Common Data Definitions 10.4 Host Controller Driver |
| 282 | 10.5 Universal Serial Bus Driver 10.5.1 USBD Overview |
| 283 | 10.5.2 USBD Command Mechanism Requirements |
| 285 | 10.5.3 USBD Pipe Mechanisms |
| 287 | 10.5.4 Managing the USB via the USBD Mechanisms |
| 289 | 10.5.5 Passing USB Preboot Control to the Operating System |
| 290 | 10.6 Operating System Environment Guides |
| 291 | 11 Chapter 11 Hub Specification 11.1 Overview 11.1.1 Hub Architecture |
| 292 | 11.1.2 Hub Connectivity |
| 294 | 11.2 Hub Frame/Microframe Timer 11.2.1 High-speed Microframe Timer Range 11.2.2 Full-speed Frame Timer Range |
| 295 | 11.2.3 Frame/Microframe Timer Synchronization |
| 297 | 11.2.4 Microframe Jitter Related to Frame Jitter 11.2.5 EOF1 and EOF2 Timing Points |
| 300 | 11.3 Host Behavior at End-of-Frame 11.3.1 Full-/low-speed Latest Host Packet 11.3.2 Full-/low-speed Packet Nullification 11.3.3 Full-/low-speed Transaction Completion Prediction |
| 301 | 11.4 Internal Port |
| 302 | 11.4.1 Inactive 11.4.2 Suspend Delay 11.4.3 Full Suspend (Fsus) 11.4.4 Generate Resume (GResume) 11.5 Downstream Facing Ports |
| 304 | 11.5.1 Downstream Facing Port State Descriptions |
| 308 | 11.5.2 Disconnect Detect Timer |
| 309 | 11.5.3 Port Indicator |
| 310 | 11.6 Upstream Facing Port 11.6.1 Full-speed |
| 311 | 11.6.2 High-speed 11.6.3 Receiver |
| 314 | 11.6.4 Transmitter |
| 315 | 11.7 Hub Repeater |
| 316 | 11.7.1 High-speed Packet Connectivity |
| 318 | 11.7.2 Hub Repeater State Machine |
| 320 | 11.7.3 Wait for Start of Packet from Upstream Port (WFSOPFU) 11.7.4 Wait for End of Packet from Upstream Port (WFEOPFU) 11.7.5 Wait for Start of Packet (WFSOP) 11.7.6 Wait for End of Packet (WFEOP) 11.8 Bus State Evaluation |
| 321 | 11.8.1 Port Error 11.8.2 Speed Detection 11.8.3 Collision |
| 322 | 11.8.4 Low-speed Port Behavior 11.9 Suspend and Resume |
| 324 | 11.10 Hub Reset Behavior |
| 325 | 11.11 Hub Port Power Control 11.11.1 Multiple Gangs |
| 326 | 11.12 Hub Controller 11.12.1 Endpoint Organization 11.12.2 Hub Information Architecture and Operation |
| 327 | 11.12.3 Port Change Information Processing |
| 328 | 11.12.4 Hub and Port Status Change Bitmap |
| 329 | 11.12.5 Over-current Reporting and Recovery |
| 330 | 11.12.6 Enumeration Handling 11.13 Hub Configuration |
| 331 | 11.14 Transaction Translator |
| 332 | 11.14.1 Overview |
| 334 | 11.14.2 Transaction Translator Scheduling |
| 336 | 11.15 Split Transaction Notation Information |
| 339 | 11.16 Common Split Transaction State Machines |
| 340 | 11.16.1 Host Controller State Machine |
| 344 | 11.16.2 Transaction Translator State Machine |
| 349 | 11.17 Bulk/Control Transaction Translation Overview |
| 350 | 11.17.1 Bulk/Control Split Transaction Sequences |
| 356 | 11.17.2 Bulk/Control Split Transaction State Machines |
| 361 | 11.17.3 Bulk/Control Sequencing |
| 362 | 11.17.4 Bulk/Control Buffering Requirements 11.17.5 Other Bulk/Control Details 11.18 Periodic Split Transaction Pipelining and Buffer Management |
| 363 | 11.18.1 Best Case Full-Speed Budget 11.18.2 TT Microframe Pipeline |
| 364 | 11.18.3 Generation of Full-speed Frames 11.18.4 Host Split Transaction Scheduling Requirements |
| 367 | 11.18.5 TT Response Generation |
| 368 | 11.18.6 TT Periodic Transaction Handling Requirements |
| 370 | 11.18.7 TT Transaction Tracking |
| 371 | 11.18.8 TT Complete-split Transaction State Searching |
| 372 | 11.19 Approximate TT Buffer Space Required 11.20 Interrupt Transaction Translation Overview 11.20.1 Interrupt Split Transaction Sequences |
| 376 | 11.20.2 Interrupt Split Transaction State Machines |
| 382 | 11.20.3 Interrupt OUT Sequencing |
| 383 | 11.20.4 Interrupt IN Sequencing |
| 384 | 11.21 Isochronous Transaction Translation Overview |
| 385 | 11.21.1 Isochronous Split Transaction Sequences |
| 388 | 11.21.2 Isochronous Split Transaction State Machines |
| 392 | 11.21.3 Isochronous OUT Sequencing |
| 393 | 11.21.4 Isochronous IN Sequencing 11.22 TT Error Handling 11.22.1 Loss of TT Synchronization With HS SOFs |
| 394 | 11.22.2 TT Frame and Microframe Timer Synchronization Requirements |
| 396 | 11.23 Descriptors 11.23.1 Standard Descriptors for Hub Class |
| 404 | 11.23.2 Class-specific Descriptors |
| 405 | 11.24 Requests 11.24.1 Standard Requests |
| 406 | 11.24.2 Class-specific Requests |
| 422 | Appendix A Transaction Examples A.1 Bulk/Control OUT and SETUP Transaction Examples |
| 446 | A.2 Bulk/Control IN Transaction Examples |
| 470 | A.3 Interrupt OUT Transaction Examples |
| 489 | A.4 Interrupt IN Transaction Examples |
| 511 | A.5 Isochronous OUT Split-transaction Examples |
| 520 | A.6 Isochronous IN Split-transaction Examples |
| 534 | Appendix B Example Declarations for State Machines B.1 Global Declarations |
| 537 | B.2 Host Controller Declarations |
| 539 | B.3 Transaction Translator Declarations |
| 543 | Appendix C Reset Protocol State Diagrams C.1 Downstream Facing Port State Diagram |
| 545 | C.2 Upstream Facing Port State Diagram |
| 550 | Index |
| 660 | 6.4.4 Prohibited Cable Assemblies |
| 661 | 11.24.3 USB Icon Location |
