BS EN 62889:2015
$142.49
Digital video interface. Gigabit video interface for multimedia systems
| Published By | Publication Date | Number of Pages |
| BSI | 2015 | 28 |
IEC 62889:2015(E) describes a serial digital interface, gigabit video interface (GVIF) for the interconnection of digital video equipment. The GVIF is primarily intended to carry high-speed digital video data for general usage and is well suited for multimedia entertainment systems in a vehicle. It specifies the physical layer of the interface including transmission line characteristics and electrical characteristics of transmitter and receiver. Mechanical and physical specifications of connectors are not included.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 4 | Foreword Endorsement notice |
| 5 | Annex ZA (normative) Normative references to international publications with their corresponding European publications |
| 6 | CONTENTS |
| 8 | FOREWORD |
| 10 | INTRODUCTION |
| 11 | 1 Scope 2 Normative references 3 Terms, definitions and abbreviations 3.1 Terms and definitions |
| 13 | 3.2 Abbreviations |
| 14 | 4 Architecture Figures FigureĀ 1 ā Architecture of the GVIF |
| 15 | 5 Electrical characteristics 5.1 DC electrical specifications FigureĀ 2 ā VOD, VOS diagram Tables TableĀ 1 ā DC electrical specifications of the transmitter |
| 16 | 5.2 AC electrical specifications FigureĀ 3 ā Transmitter eye mask specifications (TP1) TableĀ 2 ā DC electrical specifications of the receiver TableĀ 3 ā AC electrical specifications of the transmitter TableĀ 4 ā AC electrical specifications of the receiver |
| 17 | 6 Front-end 6.1 General 6.2 TX front-end 6.3 RX front-end FigureĀ 4 ā Front-end block diagram |
| 18 | 7 Transition state link FigureĀ 5 ā Transition state link |
| 19 | 8 Protocol 8.1 General 8.2 Encoder FigureĀ 6 ā Encoder output diagram |
| 20 | FigureĀ 7 ā C format word FigureĀ 8 ā H format word TableĀ 5 ā 4B5B conversion |
| 21 | 8.3 Decoder 9 Transmission system and transmission line of electrical characteristics FigureĀ 9 ā Transmission system TableĀ 6 ā VSYNC, HSYNC, DE, CNTL/AUX, SDA, TDA transition and the corresponding header |
| 22 | FigureĀ 10 ā Transmission line tolerance impedance FigureĀ 11 ā Transmission loss |
| 23 | Annex A (informative) Multiple link application A.1 Single link application example A.1.1 Block diagram for single link transmission FigureĀ A.1 ā Differential single link block diagram |
| 24 | A.1.2 Data mapping of single link transmission A.2 Multiple link application example A.2.1 Block diagram for 2-pair parallel transmission FigureĀ A.2 ā Pixel configuration FigureĀ A.3 ā Multiple link application block diagram |
| 25 | A.2.2 Data mapping of 2-pair transmission FigureĀ A.4 ā Pixel configuration when using 2-pairs |
| 26 | Bibliography |
