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BS EN IEC 61131-9:2022

BS EN IEC 61131-9:2022

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Programmable controllers – Single-drop digital communication interface for small sensors and actuators (SDCI)

Published By Publication Date Number of Pages
BSI 2022 336
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This part of IEC 61131 specifies a single-drop digital communication interface technology for small sensors and actuators SDCI (commonly known as IO-LinkTM2), which extends the traditional digital input and digital output interfaces as defined in IEC 61131-2 towards a point-to-point communication link. This technology enables the transfer of parameters to Devices and the delivery of diagnostic information from the Devices to the automation system. This technology is mainly intended for use with simple sensors and actuators in factory automation, which include small and cost-effective microcontrollers. This part specifies the SDCI communication services and protocol (physical layer, data link layer and application layer in accordance with the ISO/OSI reference model) for both SDCI Masters and Devices. This part also includes EMC test requirements. This part does not cover communication interfaces or systems incorporating multiple point or multiple drop linkages, or integration of SDCI into higher level systems such as fieldbuses.

PDF Catalog

PDF Pages PDF Title
2 undefined
5 Annex ZA (normative)Normative references to international publicationswith their corresponding European publications
7 English
CONTENTS
25 FOREWORD
27 INTRODUCTION
29 1 Scope
2 Normative references
30 3 Terms, definitions, symbols, abbreviated terms, and conventions
3.1 Terms and definitions
34 3.2 Symbols and abbreviated terms
36 3.3 Conventions
3.3.1 General
37 3.3.2 Service parameters
3.3.3 Service procedures
3.3.4 Service attributes
38 3.3.5 Figures
3.3.6 Tables
3.3.7 Transmission octet order
3.3.8 Behavioral descriptions
Figures
Figure 1 – Example of a confirmed service
Figure 2 – Memory storage and transmission order for WORD based data types
39 Figure 3 – Example of a nested state
40 4 Overview of SDCI (IO-LinkTM)
4.1 Purpose of technology
4.2 Positioning within the automation hierarchy
Figure 4 – SDCI compatibility with IEC 611312
Figure 5 – Domain of the SDCI technology within the automation hierarchy
41 4.3 Wiring, connectors and power
4.4 Communication features of SDCI
42 Figure 6 – Generic Device model for SDCI (Master’s view)
43 Figure 7 – Relationship between nature of data and transmission types
44 4.5 Role of a Master
Figure 8 – Object transfer at the application layer level (AL)
45 4.6 SDCI configuration
4.7 Mapping to fieldbuses and/or other upper-level systems
4.8 Standard structure
Figure 9 – Logical structure of Master and Device
46 5 Physical Layer (PL)
5.1 General
5.1.1 Basics
5.1.2 Topology
Figure 10 – Three wire connection system
47 5.2 Physical layer services
5.2.1 Overview
Figure 11 – Topology of SDCI
Figure 12 – Physical layer (Master)
48 5.2.2 PL services
Figure 13 – Physical layer (Device)
Tables
Table 1 – Service assignments of Master and Device
Table 2 – PL_SetMode
49 Table 3 – PL_WakeUp
Table 4 – PL_Transfer
50 5.3 Transmitter/Receiver
5.3.1 Description method
5.3.2 Electrical requirements
Figure 14 – Line driver reference schematics
Figure 15 – Receiver reference schematics
51 Figure 16 – Reference schematics for SDCI 3-wire connection system
Figure 17 – Voltage level definitions
52 Figure 18 – Switching thresholds
Table 5 – Electrical characteristics of a receiver
53 Figure 19 – Inrush current and charge (example)
Table 6 – Electrical characteristics of a Master Port
54 Table 7 – Electrical characteristics of a Device
55 5.3.3 Timing requirements
Figure 20 – Power-on timing for Power 1
Figure 21 – Format of an SDCI UART frame
Table 8 – Power-on timing
56 Figure 22 – Eye diagram for the ‘H’ and ‘L’ detection
57 Figure 23 – Eye diagram for the correct detection of a UART frame
Table 9 – Dynamic characteristics of the transmission
59 5.4 Power supply
5.4.1 Power supply options
Figure 24 – Wake-up request
Table 10 – Wake-up request characteristics
60 5.4.2 Port Class B
Figure 25 – Class A and B Port definitions
Table 11 – Electrical characteristics of a Master Port Class B
61 5.4.3 Power-on requirements
5.5 Medium
5.5.1 Connectors
Table 12 – Master pin assignments
62 5.5.2 Cable
Figure 26 – Pin layout front view
Table 13 – Device pin assignments
63 6 Standard Input and Output (SIO)
Figure 27 – Reference schematics for effective line capacitance and loop resistance
Table 14 – Cable characteristics
Table 15 – Cable conductor assignments
64 7 Data link layer (DL)
7.1 General
Figure 28 – Structure and services of the data link layer (Master)
65 7.2 Data link layer services
7.2.1 DL-B services
Figure 29 – Structure and services of the data link layer (Device)
66 Table 16 – Service assignments within Master and Device
Table 17 – DL_ReadParam
67 Table 18 – DL_WriteParam
68 Table 19 – DL_Read
Table 20 – DL_Write
69 Table 21 – DL_ISDUTransport
70 Table 22 – DL_ISDUAbort
Table 23 – DL_PDOutputUpdate
71 Table 24 – DL_PDOutputTransport
Table 25 – DL_PDInputUpdate
72 Table 26 – DL_PDInputTransport
Table 27 – DL_PDCycle
73 Table 28 – DL_SetMode
74 Table 29 – DL_Mode
Table 30 – DL_Event
75 Table 31 – DL_EventConf
Table 32 – DL_EventTrigger
Table 33 – DL_Control
76 7.2.2 DL-A services
Table 34 – DL-A services within Master and Device
77 Table 35 – OD
78 Table 36 – PD
79 Table 37 – EventFlag
Table 38 – PDInStatus
Table 39 – MHInfo
80 7.3 Data link layer protocol
7.3.1 Overview
Table 40 – ODTrig
Table 41 – PDTrig
81 7.3.2 DL-mode handler
Figure 30 – State machines of the data link layer
Figure 31 – Example of an attempt to establish communication
82 Figure 32 – Failed attempt to establish communication
83 Figure 33 – Retry strategy to establish communication
Table 42 – Wake-up procedure and retry characteristics
84 Figure 34 – Fallback procedure
Table 43 – Fallback timing characteristics
85 Figure 35 – State machine of the Master DL-mode handler
Figure 36 – Submachine 1 to establish communication
86 Table 44 – State transition table of the Master DL-mode handler
88 Figure 37 – State machine of the Device DL-mode handler
Table 45 – State transition table of the Device DL-mode handler
89 7.3.3 Message handler
90 Figure 38 – SDCI message sequences
91 Figure 39 – Overview of M-sequence types
92 Figure 40 – State machine of the Master message handler
93 Figure 41 – Submachine “Response 3” of the message handler
Figure 42 – Submachine “Response 8” of the message handler
Figure 43 – Submachine “Response 15” of the message handler
94 Table 46 – State transition table of the Master message handler
96 Figure 44 – State machine of the Device message handler
97 7.3.4 Process Data handler
Table 47 – State transition table of the Device message handler
98 Figure 45 – Interleave mode for the segmented transmission of Process Data
Figure 46 – State machine of the Master Process Data handler
99 Figure 47 – State machine of the Device Process Data handler
Table 48 – State transition table of the Master Process Data handler
100 7.3.5 On-request Data handler
Table 49 – State transition table of the Device Process Data handler
101 Figure 48 – State machine of the Master On-request Data handler
Table 50 – State transition table of the Master On-request Data handler
102 Figure 49 – State machine of the Device On-request Data handler
Table 51 – State transition table of the Device On-request Data handler
103 7.3.6 ISDU handler
Figure 50 – Structure of the ISDU
104 Table 52 – FlowCTRL definitions
105 Figure 51 – State machine of the Master ISDU handler
Table 53 – State transition table of the Master ISDU handler
106 Figure 52 – State machine of the Device ISDU handler
107 7.3.7 Command handler
Table 54 – State transition table of the Device ISDU handler
108 Figure 53 – State machine of the Master command handler
Table 55 – Control codes
Table 56 – State transition table of the Master command handler
109 Figure 54 – State machine of the Device command handler
110 7.3.8 Event handler
Table 57 – State transition table of the Device command handler
Table 58 – Event memory
111 Figure 55 – State machine of the Master Event handler
112 Figure 56 – State machine of the Device Event handler
Table 59 – State transition table of the Master Event handler
113 8 Application layer (AL)
8.1 General
Table 60 – State transition table of the Device Event handler
114 8.2 Application layer services
8.2.1 AL services within Master and Device
Figure 57 – Structure and services of the application layer (Master)
Figure 58 – Structure and services of the application layer (Device)
115 8.2.2 AL Services
Table 61 – AL services within Master and Device
Table 62 – AL_Read
116 Table 63 – AL_Write
117 Table 64 – AL_Abort
118 Table 65 – AL_GetInput
119 Table 66 – AL_NewInput
Table 67 – AL_SetInput
Table 68 – AL_PDCycle
120 Table 69 – AL_GetOutput
Table 70 – AL_NewOutput
121 Table 71 – AL_SetOutput
122 Table 72 – AL_Event
123 8.3 Application layer protocol
8.3.1 Overview
8.3.2 On-request Data transfer
Table 73 – AL_Control
124 Figure 59 – OD state machine of the Master AL
Table 74 – States and transitions for the OD state machine of the Master AL
126 Figure 60 – OD state machine of the Device AL
Table 75 – States and transitions for the OD state machine of the Device AL
127 Figure 61 – Sequence diagram for the transmission of On-request Data
128 Figure 62 – Sequence diagram for On-request Data in case of errors
Figure 63 – Sequence diagram for On-request Data in case of timeout
129 8.3.3 Event processing
Figure 64 – Event state machine of the Master AL
Table 76 – State and transitions of the Event state machine of the Master AL
130 Figure 65 – Event state machine of the Device AL
Table 77 – State and transitions of the Event state machine of the Device AL
131 Figure 66 – Single Event scheduling
132 8.3.4 Process Data cycles
Figure 67 – Sequence diagram for output Process Data
133 9 System Management (SM)
9.1 General
9.2 System Management of the Master
9.2.1 Overview
Figure 68 – Sequence diagram for input Process Data
134 Figure 69 – Structure and services of the Master System Management
135 9.2.2 SM Master services
Figure 70 – Sequence chart of the use case “Port x setup”
136 Table 78 – SM services within the Master
Table 79 – SM_SetPortConfig
137 Table 80 – Definition of the InspectionLevel (IL)
Table 81 – Definitions of the Target Modes
138 Table 82 – SM_GetPortConfig
139 Table 83 – SM_PortMode
140 9.2.3 SM Master protocol
Table 84 – SM_Operate
141 Figure 71 – Main state machine of the Master System Management
142 Table 85 – State transition table of the Master System Management
143 Figure 72 – SM Master submachine CheckCompatibility_1
144 Table 86 – State transition table of the Master submachine CheckCompatibility_1
145 Figure 73 – Activity for state “CheckVxy”
Figure 74 – Activity for state “CheckCompV10”
146 Figure 75 – Activity for state “CheckComp”
Figure 76 – Activity (write parameter) in state “RestartDevice”
147 Figure 77 – SM Master submachine checkSerNum_3
Table 87 – State transition table of the Master submachine checkSerNum_3
148 9.3 System Management of the Device
9.3.1 Overview
Figure 78 – Activity (check SerialNumber) for state CheckSerNum_31
149 Figure 79 – Structure and services of the System Management (Device)
150 9.3.2 SM Device services
Figure 80 – Sequence chart of the use case “INACTIVE – SIO – SDCI – SIO”
151 Table 88 – SM services within the Device
Table 89 – SM_SetDeviceCom
152 Table 90 – SM_GetDeviceCom
153 Table 91 – SM_SetDeviceIdent
154 Table 92 – SM_GetDeviceIdent
155 Table 93 – SM_SetDeviceMode
Table 94 – SM_DeviceMode
156 9.3.3 SM Device protocol
157 Figure 81 – State machine of the Device System Management
158 Table 95 – State transition table of the Device System Management
160 Figure 82 – Sequence chart of a regular Device startup
161 Figure 83 – Sequence chart of a Device startup in compatibility mode
162 Figure 84 – Sequence chart of a Device startup when compatibility fails
163 10 Device
10.1 Overview
Figure 85 – Structure and services of a Device
164 10.2 Process Data Exchange (PDE)
10.3 Parameter Manager (PM)
10.3.1 General
10.3.2 Parameter Manager state machine
165 Figure 86 – Parameter Manager (PM) state machine
Table 96 – State transition table of the PM state machine
167 10.3.3 Dynamic parameter
10.3.4 Single parameter
Figure 87 – Positive and negative parameter checking result
168 10.3.5 Block Parameter
Table 97 – Sequence of parameter checks
169 Figure 88 – Positive Block Parameter download with Data Storage request
170 Figure 89 – Negative Block Parameter download
Table 98 – Steps and rules for Block Parameter checking
171 10.3.6 Concurrent parameterization access
10.3.7 Command handling
Table 99 – Prioritized ISDU responses on command parameters
172 10.4 Data Storage (DS)
10.4.1 General
10.4.2 Data Storage state machine
Figure 90 – Data Storage (DS) state machine
173 Table 100 – State transition table of the Data Storage state machine
174 10.4.3 DS configuration
10.4.4 DS memory space
10.4.5 DS Index_List
Figure 91 – Data Storage request message sequence
175 10.4.6 DS parameter availability
10.4.7 DS without ISDU
10.4.8 DS parameter change indication
10.5 Event Dispatcher (ED)
10.6 Device features
10.6.1 General
10.6.2 Device backward compatibility
176 10.6.3 Protocol revision compatibility
10.6.4 Visual SDCI indication
10.6.5 Parameter access locking
10.6.6 Data Storage locking
10.6.7 Locking of local parameter entries
10.6.8 Locking of local user interface
10.6.9 Offset time
177 10.6.10 Data Storage concept
10.6.11 Block Parameter
10.7 Device reset options
10.7.1 Overview
Figure 92 – Cycle timing
178 10.7.2 Device reset
10.7.3 Application reset
Table 101 – Overview on reset options and their impact on Devices
179 10.7.4 Restore factory settings
10.7.5 Back-to-box
10.8 Device design rules and constraints
10.8.1 General
10.8.2 Process Data
180 10.8.3 Communication loss
10.8.4 Direct Parameter
10.8.5 ISDU communication channel
10.8.6 DeviceID rules related to Device variants
181 10.8.7 Protocol constants
10.9 IO Device description (IODD)
10.10 Device diagnosis
10.10.1 Concepts
Table 102 – Overview of the protocol constants for Devices
182 10.10.2 Events
Table 103 – Classification of Device diagnosis incidents
183 10.10.3 Visual indicators
Figure 93 – Event flow in case of successive errors
184 10.11 Device connectivity
11 Master
11.1 Overview
11.1.1 Positioning of Master and Gateway Applications
Figure 94 – Device LED indicator timing
Table 104 – Timing for LED indicators
185 11.1.2 Structure, applications, and services of a Master
Figure 95 – Generic relationship of SDCI and automation technology
186 11.1.3 Object view of a Master and its Ports
Figure 96 – Structure, applications and services of a Master
187 11.2 Services of the Standardized Master Interface (SMI)
11.2.1 Overview
Figure 97 – Object model of Master and Ports
Figure 98 – SMI services
188 11.2.2 Structure of SMI service arguments
Table 105 – SMI services
189 11.2.3 Concurrency and prioritization of SMI services
190 11.2.4 SMI_MasterIdentification
Table 106 – SMI_MasterIdentification
191 11.2.5 SMI_PortConfiguration
Table 107 – SMI_PortConfiguration
192 11.2.6 SMI_ReadbackPortConfiguration
193 Table 108 – SMI_ReadbackPortConfiguration
194 11.2.7 SMI_PortStatus
Table 109 – SMI_PortStatus
195 11.2.8 SMI_DSToParServ
Table 110 – SMI_DSToParServ
196 11.2.9 SMI_ParServToDS
197 Table 111 – SMI_ParServToDS
198 11.2.10 SMI_DeviceWrite
Table 112 – SMI_DeviceWrite
199 11.2.11 SMI_DeviceRead
Table 113 – SMI_DeviceRead
200 11.2.12 SMI_ParamWriteBatch
201 Table 114 – SMI_ParamWriteBatch
202 11.2.13 SMI_ParamReadBatch
Table 115 – SMI_ParamReadBatch
203 11.2.14 SMI_PortPowerOffOn
204 Table 116 – SMI_PortPowerOffOn
205 11.2.15 SMI_DeviceEvent
Table 117 – SMI_DeviceEvent
206 11.2.16 SMI_PortEvent
11.2.17 SMI_PDIn
Table 118 – SMI_PortEvent
207 Table 119 – SMI_PDIn
208 11.2.18 SMI_PDOut
Table 120 – SMI_PDOut
209 11.2.19 SMI_PDInOut
Table 121 – SMI_PDInOut
210 11.2.20 SMI_PDInIQ
211 Table 122 – SMI_PDInIQ
212 11.2.21 SMI_PDOutIQ
Table 123 – SMI_PDOutIQ
213 11.2.22 SMI_PDReadbackOutIQ
Table 124 – SMI_PDReadbackOutIQ
214 11.3 Configuration Manager (CM)
11.3.1 Coordination of Master applications
215 Figure 99 – Coordination of Master applications
Table 125 – Internal variables and Events controlling Master applications
217 11.3.2 State machine of the Configuration Manager
Figure 100 – Sequence diagram of start-up via Configuration Manager
218 Figure 101 – State machine of the Configuration Manager
Table 126 – State transition table of the Configuration Manager
221 Figure 102 – Activity for state “CheckPortMode_0”
222 11.4 Data Storage (DS)
11.4.1 Overview
11.4.2 DS data object
11.4.3 Backup and Restore
11.4.4 DS state machine
223 Figure 103 – Main state machine of the Data Storage mechanism
224 Figure 104 – Submachine “UpDownload_2” of the Data Storage mechanism
225 Figure 105 – Data Storage submachine “Upload_7”
Figure 106 – Data Storage upload sequence diagram
226 Figure 107 – Data Storage submachine “Download_10”
Figure 108 – Data Storage download sequence diagram
227 Table 127 – States and transitions of the Data Storage state machines
229 11.4.5 Parameter selection for Data Storage
11.5 On-request Data exchange (ODE)
230 11.6 Diagnosis Unit (DU)
11.6.1 General
Figure 109 – State machine of the On-request Data Exchange
Table 128 – State transition table of the ODE state machine
231 11.6.2 Device specific Events
11.6.3 Port specific Events
Figure 110 – DeviceEvent flow control
Figure 111 – Port Event flow control
232 11.6.4 Dynamic diagnosis status
11.6.5 Best practice recommendations
Figure 112 – SDCI diagnosis information propagation via Events
233 11.7 PD Exchange (PDE)
11.7.1 General
11.7.2 Process Data input mapping
Figure 113 – Principles of Process Data Input mapping
234 11.7.3 Process Data output mapping
Figure 114 – Port Qualifier Information (PQI)
235 11.7.4 Process Data invalid/valid qualifier status
Figure 115 – Principles of Process Data Output mapping
236 12 Holistic view on Data Storage
12.1 User point of view
Figure 116 – Propagation of PD qualifier status between Master and Device
237 12.2 Operations and preconditions
12.2.1 Purpose and objectives
12.2.2 Preconditions for the activation of the Data Storage mechanism
12.2.3 Preconditions for the types of Devices to be replaced
12.2.4 Preconditions for the parameter sets
238 12.3 Commissioning
12.3.1 On-line commissioning
12.3.2 Off-site commissioning
Figure 117 – Active and backup parameter
Figure 118 – Off-site commissioning
239 12.4 Backup Levels
12.4.1 Purpose
12.4.2 Overview
Table 129 – Recommended Data Storage Backup Levels
240 12.4.3 Commissioning (“Disable”)
12.4.4 Production (“Backup/Restore”)
Table 130 – Criteria for backing up parameters (“Backup/Restore”)
241 12.4.5 Production (“Restore”)
12.5 Use cases
12.5.1 Device replacement (“Backup/Restore”)
12.5.2 Device replacement (“Restore”)
12.5.3 Master replacement
Table 131 – Criteria for backing up parameters (“Restore”)
242 12.5.4 Project replication
13 Integration
13.1 Generic Master model for system integration
243 13.2 Role of gateway applications
13.2.1 Clients
13.2.2 Coordination
13.3 Security
13.4 Special gateway applications
13.4.1 Changing Device configuration including Data Storage
Figure 119 – Generic Master model for system integration
244 13.4.2 Parameter server and recipe control
13.5 Port and Device Configuration Tool (PDCT)
13.5.1 Strategy
13.5.2 Accessing Masters via SMI
13.5.3 Basic layout examples
Figure 120 – PDCT via gateway application
245 Figure 121 – Example 1 of a PDCT display layout
Figure 122 – Example 2 of a PDCT display layout
246 Annex A (normative)Codings, timing constraints, and errors
A.1 General structure and encoding of M-sequences
A.1.1 Overview
A.1.2 M-sequence control (MC)
Figure A.1 – M-sequence control
Table A.1 – Values of communication channel
247 A.1.3 Checksum/M-sequence type (CKT)
A.1.4 User data (PD or OD)
Figure A.2 – Checksum/M-sequence type octet
Table A.2 – Values of R/W
Table A.3 – Values of M-sequence types
248 A.1.5 Checksum/status (CKS)
Figure A.3 – Checksum/status octet
Table A.4 – Data types for user data
Table A.5 – Values of PD status
249 A.1.6 Calculation of the checksum
Figure A.4 – Principle of the checksum calculation and compression
Table A.6 – Values of the Event flag
250 A.2 M-sequence types
A.2.1 Overview
A.2.2 M-sequence TYPE_0
A.2.3 M-sequence TYPE_1_x
Figure A.5 – M-sequence TYPE_0
Figure A.6 – M-sequence TYPE_1_1
251 Figure A.7 – M-sequence TYPE_1_2
Figure A.8 – M-sequence TYPE_1_V
252 A.2.4 M-sequence TYPE_2_x
Figure A.9 – M-sequence TYPE_2_1
Figure A.10 – M-sequence TYPE_2_2
253 Figure A.11 – M-sequence TYPE_2_3
Figure A.12 – M-sequence TYPE_2_4
Figure A.13 – M-sequence TYPE_2_5
254 A.2.5 M-sequence type 3
A.2.6 M-sequence type usage for STARTUP, PREOPERATE and OPERATE modes
Figure A.14 – M-sequence TYPE_2_V
Table A.7 – M-sequence types for the STARTUP mode
Table A.8 – M-sequence types for the PREOPERATE mode
255 Table A.9 – M-sequence types for the OPERATE mode (legacy protocol)
Table A.10 – M-sequence types for the OPERATE mode
256 A.3 Timing constraints
A.3.1 General
A.3.2 Bit time
A.3.3 UART frame transmission delay of Master (Ports)
A.3.4 UART frame transmission delay of Devices
A.3.5 Response time of Devices
A.3.6 M-sequence time
257 A.3.7 Cycle time
Figure A.15 – M-sequence timing
Table A.11 – Recommended MinCycleTimes
258 A.3.8 Idle time
A.3.9 Recovery time
A.4 Errors and remedies
A.4.1 UART errors
A.4.2 Wake-up errors
A.4.3 Transmission errors
259 A.4.4 Protocol errors
A.5 General structure and encoding of ISDUs
A.5.1 Overview
A.5.2 I-Service
Figure A.16 – I-Service octet
260 A.5.3 Extended length (ExtLength)
Table A.12 – Definition of the nibble “I-Service”
Table A.13 – ISDU syntax
261 A.5.4 Index and Subindex
A.5.5 Data
A.5.6 Check ISDU (CHKPDU)
Table A.14 – Definition of nibble Length and octet ExtLength
Table A.15 – Use of Index formats
262 A.5.7 ISDU examples
Figure A.17 – Check of ISDU integrity via CHKPDU
Figure A.18 – Examples of request formats for ISDUs
263 Figure A.19 – Examples of response ISDUs
264 A.6 General structure and encoding of Events
A.6.1 General
A.6.2 StatusCode type 1 (no details)
Figure A.20 – Examples of read and write request ISDUs
Figure A.21 – Structure of StatusCode type 1
265 A.6.3 StatusCode type 2 (with details)
Figure A.22 – Structure of StatusCode type 2
Table A.16 – Mapping of EventCodes (type 1)
266 A.6.4 EventQualifier
Figure A.23 – Indication of activated Events
Figure A.24 – Structure of the EventQualifier
Table A.17 – Values of INSTANCE
267 A.6.5 EventCode
Table A.18 – Values of SOURCE
Table A.19 – Values of TYPE
Table A.20 – Values of MODE
268 Annex B (normative)Parameters and commands
B.1 Direct Parameter pages 1 and 2
B.1.1 Overview
Figure B.1 – Classification and mapping of Direct Parameters
269 B.1.2 MasterCommand
Table B.1 – Direct Parameter pages 1 and 2
270 B.1.3 MasterCycleTime and MinCycleTime
Figure B.2 – MinCycleTime
Table B.2 – Types of MasterCommands
271 B.1.4 M-sequenceCapability
Figure B.3 – M-sequenceCapability
Table B.3 – Possible values of MasterCycleTime and MinCycleTime
Table B.4 – Values of ISDU
272 B.1.5 RevisionID (RID)
B.1.6 ProcessDataIn
Figure B.4 – RevisionID
Figure B.5 – ProcessDataIn
273 B.1.7 ProcessDataOut
B.1.8 VendorID (VID)
B.1.9 DeviceID (DID)
B.1.10 FunctionID (FID)
Table B.5 – Values of SIO
Table B.6 – Permitted combinations of BYTE and Length
274 B.1.11 SystemCommand
B.1.12 Device specific Direct Parameter page 2
B.2 Predefined Device parameters
B.2.1 Overview
Figure B.6 – Index space for ISDU data objects
275 Table B.7 – Implementation rules for parameters and commands
Table B.8 – Index assignment of data objects (Device parameter)
277 B.2.2 SystemCommand
Table B.9 – Coding of SystemCommand (ISDU)
278 B.2.3 DataStorageIndex
Table B.10 – DataStorageIndex assignments
279 B.2.4 DeviceAccessLocks
Table B.11 – Structure of Index_List
280 Table B.12 – Device locking possibilities
281 B.2.5 ProfileCharacteristic
B.2.6 PDInputDescriptor
B.2.7 PDOutputDescriptor
B.2.8 VendorName
B.2.9 VendorText
B.2.10 ProductName
B.2.11 ProductID
B.2.12 ProductText
282 B.2.13 SerialNumber
B.2.14 HardwareRevision
B.2.15 FirmwareRevision
B.2.16 ApplicationSpecificTag
B.2.17 FunctionTag
B.2.18 LocationTag
B.2.19 ErrorCount
B.2.20 DeviceStatus
283 B.2.21 DetailedDeviceStatus
Table B.13 – DeviceStatus parameter
284 B.2.22 ProcessDataInput
B.2.23 ProcessDataOutput
B.2.24 OffsetTime
Figure B.7 – Structure of the OffsetTime
Table B.14 – DetailedDeviceStatus (Index 0x0025)
285 B.2.25 Profile parameter (reserved)
B.2.26 Preferred Index
B.2.27 Extended Index
B.2.28 Profile specific Index (reserved)
Table B.15 – Time base coding and values of OffsetTime
286 Annex C (normative)ErrorTypes (ISDU errors)
C.1 General
C.2 Application related ErrorTypes
C.2.1 Overview
Table C.1 – ErrorTypes
287 C.2.2 Device application error – no details
C.2.3 Index not available
C.2.4 Subindex not available
C.2.5 Service temporarily not available
C.2.6 Service temporarily not available – local control
C.2.7 Service temporarily not available – device control
C.2.8 Access denied
C.2.9 Parameter value out of range
C.2.10 Parameter value above limit
C.2.11 Parameter value below limit
288 C.2.12 Parameter length overrun
C.2.13 Parameter length underrun
C.2.14 Function not available
C.2.15 Function temporarily unavailable
C.2.16 Invalid parameter set
C.2.17 Inconsistent parameter set
C.2.18 Application not ready
C.2.19 Vendor specific
C.3 Derived ErrorTypes
C.3.1 Overview
289 C.3.2 Master – Communication error
C.3.3 Master – ISDU timeout
C.3.4 Device Event – ISDU error
C.3.5 Device Event – ISDU illegal service primitive
C.3.6 Master – ISDU checksum error
C.3.7 Master – ISDU illegal service primitive
C.3.8 Device Event – ISDU buffer overflow
Table C.2 – Derived ErrorTypes
290 C.4 SMI related ErrorTypes
C.4.1 Overview
C.4.2 ArgBlock unknown
C.4.3 Incorrect ArgBlock content type
C.4.4 Device not communicating
C.4.5 Service unknown
C.4.6 Process Data not accessible
C.4.7 Insufficient memory
C.4.8 Incorrect Port number
Table C.3 – SMI related ErrorTypes
291 C.4.9 Incorrect ArgBlock length
C.4.10 Master busy
C.4.11 Inconsistent DS data
C.4.12 Device or Master error
292 Annex D (normative)EventCodes (diagnosis information)
D.1 General
D.2 EventCodes for Devices
Table D.1 – EventCodes for Devices
294 D.3 EventCodes for Ports
Table D.2 – EventCodes for Ports
296 Annex E (normative)Coding of ArgBlocks
E.1 General
Figure E.1 – Assignment of ArgBlock identifiers
297 E.2 MasterIdent
Table E.1 – ArgBlock types and their ArgBlockIDs
298 E.3 PortConfigList
Table E.2 – MasterIdent
299 Table E.3 – PortConfigList
300 E.4 PortStatusList
301 Table E.4 – PortStatusList
302 E.5 On-request_Data
Table E.5 – On-request_Data
303 E.6 DS_Data
E.7 DeviceParBatch
Table E.6 – DS_Data
Table E.7 – DeviceParBatch
304 E.8 IndexList
E.9 PortPowerOffOn
E.10 PDIn
Table E.8 – IndexList
Table E.9 – PortPowerOffOn
305 E.11 PDOut
E.12 PDInOut
Table E.10 – PDIn
Table E.11 – PDOut
306 E.13 PDInIQ
E.14 PDOutIQ
Table E.12 – PDInOut
Table E.13 – PDInIQ
307 E.15 DeviceEvent
E.16 PortEvent
E.17 VoidBlock
Table E.14 – PDOutIQ
Table E.15 – DeviceEvent
Table E.16 – PortEvent
308 E.18 JobError
Table E.17 – VoidBlock
Table E.18 – JobError
309 Annex F (normative)Data types
F.1 General
F.2 Basic data types
F.2.1 General
F.2.2 BooleanT
F.2.3 UIntegerT
Table F.1 – BooleanT
Table F.2 – BooleanT coding
310 F.2.4 IntegerT
Figure F.1 – Coding example of small UIntegerT
Figure F.2 – Coding example of large UIntegerT
Table F.3 – UIntegerT
Table F.4 – IntegerT
311 Table F.5 – IntegerT coding (8 octets)
Table F.6 – IntegerT coding (4 octets)
Table F.7 – IntegerT coding (2 octets)
Table F.8 – IntegerT coding (1 octet)
312 F.2.5 Float32T
Figure F.3 – Coding examples of IntegerT
Table F.9 – Float32T
Table F.10 – Coding of Float32T
313 F.2.6 StringT
F.2.7 OctetStringT
Figure F.4 – Singular access of StringT
Table F.11 – StringT
Table F.12 – OctetStringT
314 F.2.8 TimeT
Figure F.5 – Coding example of OctetStringT
Figure F.6 – Definition of TimeT
Table F.13 – TimeT
315 F.2.9 TimeSpanT
Table F.14 – Coding of TimeT
Table F.15 – TimeSpanT
Table F.16 – Coding of TimeSpanT
316 F.3 Composite data types
F.3.1 General
F.3.2 ArrayT
F.3.3 RecordT
Figure F.7 – Example of an ArrayT data structure
Table F.17 – Structuring rules for ArrayT
Table F.18 – Example for the access of an ArrayT
317 Table F.19 – Structuring rules for RecordT
Table F.20 – Example 1 for the access of a RecordT
Table F.21 – Example 2 for the access of a RecordT
318 Figure F.8 – Example 2 of a RecordT structure
Figure F.9 – Example 3 of a RecordT structure
Table F.22 – Example 3 for the access of a RecordT
319 Figure F.10 – Write requests for Example 3
320 Annex G (normative)Structure of the Data Storage data object
Table G.1 – Structure of the stored DS data object
Table G.2 – Associated header information for stored DS data objects
321 Annex H (normative)Master and Device conformity
H.1 Electromagnetic compatibility (EMC) requirements
H.1.1 General
H.1.2 Operating conditions
H.1.3 Performance criteria
322 H.1.4 Required immunity tests
Table H.1 – EMC test conditions for SDCI
Table H.2 – EMC test levels
323 H.1.5 Required emission tests
H.1.6 Test configurations for Master
324 Figure H.1 – Test setup for electrostatic discharge (Master)
Figure H.2 – Test setup for RF electromagnetic field (Master)
Figure H.3 – Test setup for fast transients (Master)
325 H.1.7 Test configurations for Devices
Figure H.4 – Test setup for RF common mode (Master)
Figure H.5 – Test setup for electrostatic discharges (Device)
326 H.2 Test strategies for conformity
H.2.1 Test of a Device
Figure H.6 – Test setup for RF electromagnetic field (Device)
Figure H.7 – Test setup for fast transients (Device)
Figure H.8 – Test setup for RF common mode (Device)
327 H.2.2 Test of a Master
328 Annex I (informative)Residual error probabilities
I.1 Residual error probability of the SDCI data integrity mechanism
I.2 Derivation of EMC test conditions
Figure I.1 – Residual error probability for the SDCI data integrity mechanism
330 Annex J (informative)Example sequence of an ISDU transmission
Figure J.1 – Example for ISDU transmissions (1 of 2)
332 Annex K (informative)Recommended methods for detecting parameter changes
K.1 CRC signature
K.2 Revision counter
Table K.1 – Proper CRC generator polynomials
333 Bibliography

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BS EN IEC 61131-9:2022
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