BS EN IEC 62228-6:2022
$152.82
Integrated circuit. EMC evaluation of transceivers – PSI5 transceivers
Published By | Publication Date | Number of Pages |
BSI | 2022 | 56 |
This document specifies test and measurement methods for EMC evaluation of Peripheral Sensor Interface 5 (PSI5) transceiver integrated circuits (ICs) under network condition. It defines test configurations, test conditions, test signals, failure criteria, test procedures, test setups and test boards. It is applicable for PSI5 satellite ICs (e.g. sensors) and ICs with embedded PSI5 transceivers (e.g. PSI5 Electronic control unit IC). The document covers – the emission of RF disturbances, – the immunity against RF disturbances, – the immunity against impulses and – the immunity against electrostatic discharges (ESD).
PDF Catalog
PDF Pages | PDF Title |
---|---|
2 | undefined |
5 | Annex ZA (normative)Normative references to international publicationswith their corresponding European publications |
6 | Blank Page |
7 | English CONTENTS |
10 | FOREWORD |
12 | 1 Scope 2 Normative references |
13 | 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions 3.2 Abbreviated terms 4 General |
14 | Figures Figure 1 ā PSI5 system overview Tables Table 1 ā PSI5 physical layer electrical characteristics |
15 | Figure 2 ā Example PSI5 wiring diagram with a single sensor and equivalent model Table 2 ā Overview of required measurements and tests |
16 | 5 Test and operating conditions 5.1 Supply and ambient conditions 5.2 Test operation modes Table 3 ā Supply and ambient conditions for functional operation |
17 | Figure 3 ā PSI5-A configuration with a single sensor connection with two wires Figure 4 ā PSI5-P configuration with two sensor connection |
18 | 5.3 Test configuration 5.3.1 General test configuration for functional test Figure 5 ā General test configuration for tests in functional operation modes Table 4 ā Sensor sink current specification |
19 | 5.3.2 General test configuration for unpowered ESD test 5.3.3 Coupling ports for functional tests Figure 6 ā General test configuration for unpowered ESD test of an ECU IC Figure 7 ā General test configuration for unpowered ESD test of a satellite IC |
20 | Figure 8 ā Coupling ports for transceiver emission and immunity tests Table 5 ā Definitions for component values of coupling portsfor transceiver emission and immunity tests |
21 | 5.3.4 Coupling ports for unpowered ESD tests Figure 9 ā Coupling ports for unpowered ESD tests |
22 | 5.4 Test signals 5.4.1 General 5.4.2 Test signals for Asynchronous mode Table 6 ā Definitions of coupling ports for unpowered ESD tests |
23 | Table 7 ā Communication test signal TX1 for Asynchronous mode (125 kbps) |
24 | Table 8 ā Communication test signal TX2 for Asynchronous mode (189 kbps) |
25 | 5.4.3 Test signal for Synchronous parallel bus mode Table 9 ā Communication test signal TX3 for Asynchronous low-power mode |
26 | 5.5 Evaluation criteria 5.5.1 General Table 10 ā Communication test signal TX4 for Synchronous parallel bus mode Table 11 ā Communication test signal TX5 for Synchronous parallel bus mode |
27 | 5.5.2 Evaluation criteria in functional operation modes during exposure to disturbances 5.5.3 Evaluation criteria in unpowered condition after exposure to disturbances Table 12 ā Evaluation criteria for standalone and embedded PSI5transceiver IC in functional operation modes |
28 | 6 Test and measurement 6.1 Emission of RF disturbances 6.1.1 Test method 6.1.2 Test setup Figure 10 ā Example drawing of the maximum deviation on an IV characteristic |
29 | Figure 11 ā Test setup for measurement of RF disturbances |
30 | 6.1.3 Test procedure and parameters 6.2 Immunity to RF disturbances 6.2.1 Test method 6.2.2 Test setup Table 13 ā Parameters for emission measurements Table 14 ā Settings of the RF measurement equipment |
31 | Figure 12 ā Test setup for DPI tests |
32 | 6.2.3 Test procedure and parameters Table 15 ā Specifications for DPI tests |
33 | Table 16 ā Required DPI tests for functional status class AIC evaluation of Standard PSI5 transceiver ICs and embedded PSI5 transceiver ICs Table 17 ā Required DPI tests for functional status class CIC or DIC evaluation of standard PSI5 transceiver ICs and ICs with embedded PSI5 transceiver |
34 | 6.3 Immunity to impulses 6.3.1 Test method 6.3.2 Test setup Figure 13 ā Test setup for impulse immunity tests |
35 | 6.3.3 Test procedure and parameters Table 18 ā Specifications for impulse immunity tests |
36 | Table 19 ā Parameters for impulse immunity test Table 20 ā Required impulse immunity tests for functional status class AIC evaluation of standard and embedded PSI5 transceiver ICs Table 21 ā Required impulse immunity tests for functional status class CIC or DIC evaluation of Standard PSI5 transceiver ICs and ICs with embedded PSI transceiver |
37 | 6.4 Electrostatic discharge (ESD) 6.4.1 Test method 6.4.2 Test setup |
38 | Figure 14 ā Test setup for direct ESD tests |
39 | 6.4.3 Test procedure and parameters |
40 | 7 Test report Table 22 ā Specifications for direct ESD tests |
41 | Annex A (normative)PSI5 test circuits A.1 General A.2 Test circuit for emission and immunity tests on a PSI5 ECU IC |
43 | Figure A.1 ā General circuit diagram of the PSI5 test networkfor emission and immunity tests on ECU IC |
44 | A.3 Test circuit for emission and immunity tests on a PSI5 satellite IC |
45 | Figure A.2 ā General circuit diagram of the PSI5 test networkfor emission and immunity tests on Satellite IC |
46 | A.4 Test circuit for an unpowered ESD test on a PSI5 IC Figure A.3 ā General circuit diagram of the PSI5 ECU ICfor testing of direct ESD in unpowered mode |
47 | Figure A.4 ā General circuit diagram of the PSI5 sensor ICfor testing of direct ESD in unpowered mode |
48 | Annex B (normative)Test circuit boards B.1 Test circuit board for emission and immunity tests B.2 ESD test Table B.1 ā Parameter ESD test circuit board |
49 | Annex C (informative)Examples of test limits for PSI5 transceiver in automotive applications C.1 General C.2 Emission of RF disturbances Figure C.1 ā Example of limits for RF emission ā PSI5 pins |
50 | C.3 Immunity to RF disturbances Figure C.2 ā Example of limits for RF emission ā Other global pins |
51 | Figure C.3 ā Example of limits for RF immunity for functional status class AIC ā PSI5 pins Figure C.4 ā Example of limits for RF immunity for functional status class AIC ā Other global pins |
52 | Figure C.5 ā Example of limits for RF immunity for functional status class CIC or DIC ā PSI5 pins Figure C.6 ā Example of limits for RF immunity for functional status class CIC or DIC ā Other global pins |
53 | C.4 Immunity to Impulses C.5 ESD Table C.1 ā Example of limits for impulse immunity for functional status class CIC or DIC |
54 | Bibliography |