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BS EN IEC 62680-4-1:2022

BS EN IEC 62680-4-1:2022

$215.11

Universal Serial Bus interfaces for data and power – Universal Serial Bus 4 ™ Specification

Published By Publication Date Number of Pages
BSI 2022 608
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The specification is primarily targeted at peripheral developers and platform/adapter developers, but provides valuable information for platform operating system/BIOS/device driver, adapter independent hardware vendors/independent software vendors, and system OEMs. This specification can be used for developing new products and associated software.

PDF Catalog

PDF Pages PDF Title
2 undefined
4 European foreword
Endorsement notice
5 FOREWORD
18 CONTENTS
44 1 Introduction
1.1 Scope of the Document
1.2 USB Product Compliance
1.3 Document Organization
1.4 Design Goals
1.5 Related Documents
45 1.6 Conventions
1.6.1 Precedence
1.6.2 Keywords
46 1.6.3 Capitalization
1.6.4 Italic Text
1.6.5 Numbering
1.6.6 Bit, Byte, DW, and Symbol Conventions
1.6.7 Implementation Notes
1.6.8 Connection Manager Notes
1.6.9 Pseudocode
47 1.6.10 CRC Algorithms
1.6.11 FourCC
1.7 Reserved Values and Fields
Tables
Table 11. Rsvd Value and Field Handling
48 1.8 Terms and Abbreviations
53 2 Architectural Overview
2.1 USB4 System Description
54 Figures
Figure 21. USB4/USB3.2 Dual Bus System Architecture
55 2.1.1 Architectural Constructs
56 Figure 22. Single-Lane USB4 Link
Figure 23. Dual-Lane USB4 Link
57 Figure 24. Example of a USB4-Based Dock
58 2.1.2 USB4 Mechanical
2.1.3 USB4 Power
2.1.4 USB4 System Configuration
2.1.5 Thunderbolt™ 3 (TBT3) Compatibility Support
59 2.1.6 USB Type-C Alternate Mode Compatibility Support
2.2 USB4 Fabric Architecture
2.2.1 USB4 Functional Stack
Figure 25. USB4 Functional Stack Layers
60 Figure 26. USB4 Port (Lane Adapter), Protocol Adapter and Control Adapter across Functional Layers
61 2.2.2 USB4 Fabric Topology
Figure 27. Example USB4 Physical Topology (No Loop) and Spanning Tree
62 2.2.3 Paths
Figure 28. Example USB4 Physical Topology (with Loop) and Spanning Tree
63 Figure 29. Paths across a USB4 Fabric
64 2.2.4 Communication Constructs
Figure 210. USB4 Communication by Functional Layer
65 Figure 211. Example Control Packet Traversing Several Routers
66 2.2.5 USB4 Host-to-Host Communications
2.2.6 Programming Model
Figure 212. Example USB4 Host-to-Host Connections
67 2.2.7 Time Synchronization
2.2.8 USB4 Fabric Data Integrity
68 2.2.9 Global Life of a Router
2.2.10 Protocol Tunneling
69 Figure 213 Example of a USB4 Host with USB3 Tunneling Highlighted
70 Figure 214. Example of a USB4 Hub with USB3 Tunneling Highlighted
Figure 215. Example of a USB4 Peripheral Device with USB3 Tunneling Highlighted
71 Figure 216. Protocol Stack for USB3 Tunneling
72 Figure 217. Example of a USB4 Fabric with USB3 Tunneling
73 Figure 218. Protocol Stacks along a USB3 Tunnel
Figure 219. Example Topology for DisplayPort Tunneling
74 Figure 220. DP IN and OUT Protocol Adapters in LTTPR Non-Transparent and LTTPR Transparent Modes
75 Figure 221. DP IN and OUT Protocol Adapters in Non-LTTPR Mode
76 Figure 222. Protocol Stacks along a DisplayPort Tunneled Path
77 Figure 223. Example Structure of a USB4 Host with PCIe Tunneling Highlighted
Figure 224. Example USB4 Hub with PCIe Tunneling Highlighted
78 Figure 225. Example USB4 Device with PCIe Tunneling Highlighted
Figure 226. Protocol Stack for PCIe Tunneling
79 Figure 227. Example of a USB4 Fabric with PCIe Tunneling
80 Figure 228. Protocol Stacks along a PCIe Tunnel
81 Figure 229. Protocol Stacks along a Path between Hosts
82 3 Electrical Layer
Figure 230. Descriptor Ring and Data Buffers
83 3.1 Sideband Channel Electrical Specifications
84 3.2 USB4 Ecosystem
3.2.1 Insertion-Loss Considerations (Informative)
Table 31. SBTX and SBRX Specifications
85 3.2.2 Coded Bit-Error-Ratio Considerations (Informative)
3.3 USB4 Electrical Compliance Methodology
3.3.1 System Compliance Test Point Definitions
Figure 31. Combined Forward-Error-Correction and Pre-Coding Scheme
86 3.3.2 AC Coupling Capacitors
Figure 32. Compliance Points Definition
Figure 33. Examples for AC-Coupling Capacitor Placement
Table 32. Electrical Compliance Test Points
87 3.3.3 Reference Clock-and-Data-Recovery (CDR) Function
3.3.4 Reference Equalization Function
Figure 34. Jitter Transfer Function
88 Figure 35. Reference Receiver Equalization
89 Figure 36. Frequency Response of Gen 2 Reference CTLE
Figure 37. Frequency Response of Gen 3 Reference CTLE
90 3.3.5 Time Domain Measurements
3.3.6 Compliance Boards
3.4 Router Assembly Transmitter Compliance
3.4.1 Transmitter Specifications Applied for All Speeds
91 Table 33. Transmitter Specifications Applied for All Speeds (at TP2)
92 Table 34. Transmitter Frequency Variation Limits During Link Training Before Obtaining Steady-State
93 Figure 38. Router Assembly Transmitter Frequency Variation During Training
Figure 39. Example Transmitter Frequency During Steady-State
94 Figure 310. TX Differential Return Loss Mask
95 Figure 311. TX Common-Mode Return Loss Mask
96 Figure 312. Transmitter Equalizer Structure
Table 35. Transmit Equalization Presets
97 Figure 313. Transmitter Equalization Frequency Response for Gen 2 Systems
98 3.4.2 Transmitter Compliance Specifications for Gen 2
Table 36. Gen 2 Transmitter Specifications at TP2
99 Table 37. Gen 2 Transmitter Specifications at TP3
100 3.4.3 Transmitter Compliance Specifications for Gen 3 Interconnects
Figure 315. TX Mask Notations
Table 38. Gen 3 Transmitter Specifications at TP2
101 3.5 Router Assembly Receiver Compliance
3.5.1 Receiver Specifications Applied for All Speeds
Table 39. Gen 3 Transmitter Specifications at TP3
Table 310. Common Receiver Specifications at TP3’
103 Figure 316. RX Differential Return-Loss Mask
104 3.5.2 Receiver Uncoded BER Tolerance Testing
Figure 317. RX Common Mode Return-Loss Mask
105 Figure 318. Receiver Tolerance Test Topologies
Figure 319. Receiver Tolerance Test Setups
106 3.5.3 Receiver Multi Error-Bursts Testing
Table 311. Stressed Signal for Gen 2 Receiver Compliance Testing
Table 312. Stressed Signal for Gen 3 Receiver Compliance Testing
108 3.6 Captive Device Compliance
3.6.1 Captive Device Compliance Test Setup
3.6.2 Captive Device Transmitter Specifications
Figure 320. Captive Device Compliance Test Setup
Table 313. Wireless Band Conducted Limits (at TP3)
109 Table 314. Captive Device Transmitter Specifications at TP3 Applied for All Speeds
110 Table 315. Captive Device Transmitter Specifications at TP3 for Gen 2 Systems
111 Table 316. Captive Device Transmitter Specifications at TP3 for Gen 3 Systems
112 3.6.3 Captive Device Receiver Specifications
Table 317. Common Receiver Specifications at TP2
114 3.6.4 Captive Device Receiver Uncoded BER Tolerance Testing
Table 318. Stressed Receiver Conditions for Gen 2 Captive Device Compliance Testing (at TP2)
Table 319. Stressed Receiver Conditions for Gen 3 Captive Device Compliance Testing (at TP2)
115 3.6.5 Captive Device Receiver Multi Error-Bursts Testing
Figure 321. Captive Device Receiver Test Setup
116 3.7 Low Frequency Periodic Signaling (LFPS)
3.7.1 LFPS Signal Definition
Table 320. LFPS Electrical Specifications
117 3.8 Receiver Lane Margining (Testability)
3.8.1 Background
Figure 322. Signaling During Power Management State Exit
118 Figure 323. Software Margining Mode Example
119 3.8.2 Receiver Voltage Margining and Timing Margining Requirements
Figure 324. Hardware Margining Flow
Table 321. RX Margining Voltage and Timing Requirements
120 Figure 325. RX Margining Range Requirements
121 3.8.3 Receiver Parameter Access
Figure 326. Optional RX Margining Range Capabilities
Table 322. Optional RX Margining Voltage Capabilities
122 4 Logical Layer
4.1 Sideband Channel
123 4.1.1 Transactions
Figure 41. Cable Topologies (Informative)
124 Figure 42. Symbol and Bit Order on Sideband Channel
Table 41. LT Transaction Format
Table 42. LSE Symbol
125 Table 43. AT Transaction Format
Table 44. STX Symbol for an AT Transaction
126 Table 45. Broadcast RT Transaction Format
Table 46. STX Symbol for a Broadcast RT Transaction
Table 47. Contents of Byte 2 in a Broadcast RT Transaction
127 Figure 43. Propagation of a Broadcast RT Transaction
Table 48. Contents of Byte 3 in a Broadcast RT Transaction
Table 49. Addressed RT Transaction Format
128 Table 410. STX Symbol for an Addressed RT Transaction
130 Figure 44. Sideband Channel Receive Transaction State Machine
131 Table 411. Sideband Channel Receive Transaction State Machine
132 Table 412. AT/RT Command Data Symbols
Table 413. AT/RT Response Data Symbols
Table 414. Processing of a Received AT/RT Command
135 Table 415. SB Registers
Table 416. SB Register Fields Access Types
Table 417. SB Register Fields
139 4.1.2 Lane Initialization
140 Figure 45. Overview of Lane Initialization
141 Figure 46. Example of Lane Reversal
142 Table 418. Lane Attributes
144 Figure 47. Progression of Link Equalization
146 4.2 Logical Layer State Machine
4.2.1 Lane Adapter State Machine
Figure 48. The Lane Adapter State Machine
148 Figure 49. Training Sub-State Machine
149 Table 419. Transmitter Behavior in Training Sub-states
Table 420. Training Sub-State Machine Transitions
151 Table 421. SLOS1 (64b/66b Encoding)
152 Table 422. SLOS2 (64b/66b Encoding)
153 Table 423. SLOS1 (128b/132b Encoding)
154 Table 424. SLOS2 (128b/132b Encoding)
Table 425. TS1 and TS2 Ordered Sets
156 Figure 410. Lane Bonding Sub-State Machine
Table 426. Transmitter Behavior in Bonding Sub-States
Table 427. Lane Bonding Sub-State Machine Transitions
157 Table 428. CL2_REQ Ordered Set
158 Table 429. CL1_REQ Ordered Set
Table 430. CL2_ACK Ordered Set
Table 431. CL1_ACK Ordered Set
Table 432. CL0s_ACK Ordered Set
Table 433. CL_NACK Ordered Set
159 Table 434. CL_OFF Ordered Set
160 Figure 411. Structure of a CL_WAKE1.X Ordered Set Symbol
173 4.2.2 USB4 Link Transitions
176 4.2.3 Logical Layer Link State
4.3 USB4 Link Encoding
177 Figure 412. Packet Flow in the Logical Layer
178 4.3.1 Lane Distribution
Figure 413. Byte Transmission Order on Lanes
179 4.3.2 Symbol Encoding
Figure 414. Byte Ordering of Transport Layer Packets to the Logical Layer
Figure 415. Byte Ordering of Idle Packets to the Logical Layer
180 4.3.3 Ordered Sets
Figure 416. Symbol Encoding of Data Symbols
Table 435. Ordered Set Structure
181 4.3.4 Bit Swap
Figure 417. Symbol Encoding of Ordered Set Symbols
182 Figure 418. Bit and Byte Ordering on the Wire – Data Symbol Payload
183 4.3.5 Scrambling
Figure 419. Bit and Byte Ordering on the Wire – Ordered Set Symbol Payload
Table 436. Scrambling Rules
184 4.3.6 RS-FEC
186 Figure 420. RS-FEC Data Structures
187 4.4 USB4 Link Operation
4.4.1 Start of Data
4.4.2 Error Cases and Recovery
Table 437. START_RS_FEC Bit Sequence
188 Table 438. Error Cases and Impact on Logical Layer
189 4.4.3 Clock Compensation and SKIP
4.4.4 Dual-Lane Skew
Table 439. SKIP Ordered Set
190 4.4.5 Disconnect
Table 440. De-Skew Ordered Set
193 4.4.6 Lane Adapter Disable and Enable
195 Figure 421. Lane Disable of the Upstream Adapter
196 Figure 422. Lane Disable Flow
197 4.4.7 Time Sync Notification Ordered Set (TSNOS)
4.5 Sleep and Wake
4.5.1 Entry to Sleep
Table 441. TSN Ordered Set
199 4.5.2 Behavior in Sleep State
4.5.3 Wake Events
Table 442. Router State Retained During Sleep
200 4.5.4 Exit from Sleep
Table 443. Wake Events
201 4.6 Timing Parameters
Table 444. Logical Layer Timing Parameters
204 5 Transport Layer
5.1 Transport Layer Packets
5.1.1 Bit/Byte Conventions
205 5.1.2 Format
Figure 51. Convention for Transport Layer Diagrams
Figure 52. Transport Layer Packet Format
Table 51. Transport Layer Packet Header Format
207 5.1.3 Transport Layer Packets
208 Figure 53. Idle Packet Contents
Table 52. Credit Grant Packet Header
Table 53. Credit Grant Record Format
209 Figure 54. Credit Grant Packet Format
Figure 55. Path Credit Sync Packet Format
Table 54. Path Credit Sync Packet Header
Table 55. Path Credit Sync Packet Payload
210 5.1.4 Effect of Link State on Transport Layer Packets
Figure 56. Shared Buffers Credit Sync Packet Format
Table 56. Shared Buffers Credit Sync Packet Header
Table 57. Shared Buffers Credit Sync Packet Payload
Table 58. Transport Layer Behavior per Link State
211 5.1.5 Minimum Headers Gap
Table 59. Minimum Transport Layer Header Gap Requirements
212 5.2 Routing
5.2.1 Adapter Numbering Rules
Figure 57. Two Concurrent Data Symbols Example
213 5.2.2 HopID Rules
214 5.2.3 Routing Tables
215 5.2.4 Routing Rules
Figure 58. Routing Table
217 5.2.5 Connectivity Rules
Figure 59. Routing Example
218 5.3 Quality of Service (QOS)
5.3.1 Packet Ordering
5.3.2 Flow Control
Figure 510. Example of Connectivity for USB3 Adapters
219 Table 510. Ingress Adapter Flow Control Schemes
220 Table 511. Buffer Allocation Parameters
224 Table 512. Egress Adapter Flow Control Schemes
226 5.3.3 Bandwidth Arbitration and Priority
227 Figure 511. Egress Adapter Scheduler
228 5.3.4 Packet Forwarding Delay Jitter
5.4 Path Tear-down
5.4.1 Egress Adapter
229 5.4.2 Ingress Adapter
5.5 Timing Parameters
Table 513. Transport Layer Timing Parameters
230 6 Configuration Layer
6.1 Domain Topology
6.2 Router Addressing
231 Figure 61. Example of TopologyID Assignment
232 6.3 Router States
Figure 62. Host Router State Machine
233 6.3.1 Uninitialized Unplugged State
6.3.2 Uninitialized Plugged State
6.3.3 Sleep State
6.3.4 Enumerated State
234 6.4 Control Packet Protocol
6.4.1 Control Adapter
6.4.2 Control Packets
Table 61. Control Packet Payload
235 Table 62. Content of a Read Request
237 Table 63. Content of a Read Response
238 Table 64. Content of a Write Request
240 Table 65. Content of a Write Response
241 Table 66. Content of a Notification Packet
242 Table 67. Content of a Notification Acknowledgement Packet
Table 68. Content of a Hot Plug Event Packet
243 Table 69. Content of an Inter-Domain Request
244 Table 610. Content of an Inter-Domain Response
245 6.4.3 Control Packet Routing
248 6.4.4 Control Packet Reliability
249 6.5 Notification Events
Table 611. Notification Events
250 6.6 Notification Acknowledgement
6.7 Router Enumeration and Initialization
252 6.8 Hot Plug and Hot Unplug Events
254 6.8.1 Router Hot Plug
6.8.2 Router Hot Unplug
255 6.9 Downstream Facing Port Reset
6.10 Timing Parameters
Table 612. Configuration Layer Timing Parameters
256 7 Time Synchronization
7.1 Time Synchronization Architecture
7.1.1 Synchronization Hierarchy
257 7.1.2 Time Sync Parameters
Figure 71. Time Synchronization Hierarchy within a Domain (Informative)
258 Figure 72. Local Time Counter Format
Figure 73. TimeOffsetFromHR Register Format
259 7.2 Time Stamp Measurement
7.2.1 Asymmetry Corrections
Figure 74. FreqOffsetFromHR Register Format
Figure 75. Time Measurement Model for 64/66b Encoding
260 7.3 Time Sync Protocol
7.3.1 Time Sync Handshake
261 Figure 76. Bi-Directional Time Sync Handshake
262 Table 71. Bidirectional UFP Timeout Values
263 Figure 77. UFP State Machine for Bi-Directional Time Sync Handshake (Recommended)
Table 72. Bidirectional DFP Timeout Values
264 Figure 78. DFP State Machine for Bi-Directional Time Sync Handshake (Recommended)
265 Figure 79. Uni-Directional Time Sync Handshake
266 Figure 710. DFP State Machine for Uni-Directional Time Sync Handshake (Recommended)
267 7.3.2 Inter-Domain Time Sync
Figure 711. UFP State Machine for Uni-Directional Time Sync Handshake (Recommended)
269 7.3.3 Packet Formats
Figure 712. Inter-Domain Time Sync Protocol (Informative)
270 Figure 713. Follow-Up Packet Format
Table 73. Follow-Up Packet Payload
272 7.4 Time Computations
Figure 714. Inter-Domain Time Stamp Packet Format
Table 74. Inter-Domain Time Stamp Packet Payload
273 Table 75. Definition of Variables
Table 76. Index Notation
274 7.4.1 Intra-Domain Equations
Figure 715. Inter-Domain Topology (Informative)
276 7.4.2 Inter-Domain Equations
280 7.4.3 Filtering
Figure 716. Filter Attenuation
281 7.5 Time Synchronization Accuracy Requirements
7.5.1 Paired Measurement
7.5.2 Standalone Measurement
Figure 717. Dynamic Noise Types
282 7.5.3 Measuring Method
Figure 718. Standalone Measurement Points
283 7.5.4 Accuracy Parameters
Figure 719. Time Events
Figure 720. Measuring Method
284 7.6 Software Configuration
7.6.1 Intra-Domain Time Synchronization Setup
7.6.2 Inter-Domain Time Synchronization Setup
7.6.3 Post Time Mechanism
Table 77. Time Synchronization Accuracy Parameters
285 7.6.4 Time Disruption Bit
286 8 Configuration Spaces
8.1 Configuration Fields Access Types
Table 81. Configuration Register Fields Access Types
287 8.2 Configuration Spaces
8.2.1 Router Configuration Space
288 Figure 81. Structure of the Router Configuration Space
Table 82. List of Router Configuration Capabilities
289 Table 83. Router Configuration Space Basic Attributes
296 Figure 82. UUID Format
297 Figure 83. Structure of the TMU Router Configuration Capability
298 Table 84. TMU Router Configuration Capability Fields
303 Table 85. Locked Registers Groups
304 Figure 84. Structure of a Vendor Specific Capability
Figure 85. Structure of a Vendor Specific Extended Capability
Table 86. Vendor Specific Capability Fields
305 8.2.2 Adapter Configuration Space
Table 87. Vendor Specific Extended Capability Fields
306 Figure 86. Structure of the Adapter Configuration Space
Table 88. List of Adapter Configuration Capabilities
307 Figure 87. Basic Configuration Registers of the Adapter Configuration Space
Table 89. Adapter Configuration Space Basic Attributes
311 Figure 88. Structure of the TMU Adapter Configuration Capability
Table 810. Adapter Types
312 Table 811. TMU Adapter Configuration Capability Fields
314 Figure 89. Structure of the Lane Adapter Configuration Capability
Table 812. Contents of the Lane Adapter Configuration Capability
317 Figure 810. Structure of USB4 Port Capability
318 Table 813. USB4 Port Capability Fields
323 Figure 811. Structure of USB3 Adapter Configuration Capability
Table 814. USB3 Adapter Configuration Capability Fields
326 Figure 812. Structure of DP IN Adapter Configuration Capability
Table 815. DP IN Adapter Configuration Capability Fields
333 Figure 813. Structure of DP OUT Adapter Configuration Capability
Table 816. DP OUT Adapter Configuration Capability Fields
338 Figure 814. Structure of PCIe Adapter Configuration Capability
Table 817. PCIe Adapter Configuration Capability Fields
339 8.2.3 Path Configuration Space
Figure 815. Structure of Path 0 Entry Configuration Space
340 Figure 816. Structure of Path Entry ‘n’ in Path Configuration Space at Lane Adapter
Table 818. Contents of Path 0 Entry
341 Table 819. Contents of Path Entry in Path Configuration Space at Lane Adapter
342 Figure 817. Structure of Path Entry ‘n’ in Path Configuration Space of a Protocol Adapter
Table 820. Contents of Path Entry in Path Configuration Space of a Protocol Adapter
345 8.2.4 Counters Configuration Space
Figure 818. Configuration of a Path
346 Figure 819. Structure of the Counters Configuration Space
Table 821. Counter Set Fields
347 8.3 Operations
8.3.1 Router Operations
348 Table 822. List of Router Operations
349 Table 823. Query DP Resource Availability Operation Metadata
Table 824. Query DP Resource Availability Completion Metadata and Status
Table 825. Allocate DP Resource Operation Metadata
350 Table 826. Allocate DP Resource Completion Metadata and Status
Table 827. De-Allocate DP Resource Operation Metadata
Table 828. De-Allocate DP Resource Completion Metadata and Status
351 Table 829. NVM Set Offset Operation Metadata
352 Table 830. NVM Set Offset Completion Metadata and Status
Table 831. NVM Write Operation Data
353 Table 832. NVM Write Completion Status
Table 833. NVM Authenticate Write Completion Status
354 Table 834. NVM Read Operation Metadata
Table 835. NVM Read Router Completion Metadata
Table 836. NVM Read Router Completion Data
355 Table 837. DROM Read Router Operation Metadata
Table 838. DROM Read Router Completion Metadata and Status
Table 839. DROM Read Router Completion Data
356 Table 840. Get NVM Sector Size Completion Metadata and Status
357 Table 841. Get PCIe Downstream Entry Mapping Completion Metadata and Status
Table 842. Get PCIe Downstream Entry Mapping Completion Data
358 Table 843. Get Capabilities Operation Metadata
Table 844. Get Capabilities Operation Completion Metadata and Status
359 Figure 820. Get Capabilities Operation Data Response for Capability Index 0
Table 845. List of Capabilities
360 Table 846. Set Capabilities Operation Metadata
Table 847. List of Capabilities
Table 848. Set Capabilities Operation Completion Status
361 Table 849. Buffer Allocation Request Router Completion Status and Metadata
Table 850. Buffer Allocation Request Router Completion Data DW Structure
362 Table 851. Get Container-ID Router Completion Status
Table 852. Get Container-ID Router Completion Data DW Structure
Table 853. Block Sideband Port Operation Completion Status
363 8.3.2 Port Operations
Table 854. Unblock Sideband Port Operation Completion Status
365 Table 855. List of Port Operations
368 Table 856. SET_TX_COMPLIANCE Operation Metadata
370 Table 857. SET_RX_COMPLIANCE Operation Metadata
371 Table 858. START_BER_TEST Operation Metadata
Table 859. END_BER_TEST Operation Metadata
372 Table 860. END_BER_TEST Completion Data
373 Table 861. END_BURST_TEST Operation Metadata
Table 862. END_BURST_TEST Completion Data
374 Table 863. READ_BURST_TEST Operation Metadata
Table 864. READ_BURST_TEST Completion Data
375 Table 865. ENTER_EI_TEST Operation Metadata
Table 866. ROUTER_OFFLINE_MODE Operation Metadata
377 Table 867. READ_LANE_MARGIN_CAP Completion Data
379 Table 868. RUN_HW_LANE_MARGINING Operation Metadata
Table 869. Contents Selection for RUN_HW_LANE_MARGINING Completion Data
380 Table 870. RUN_HW_LANE_MARGINING Completion Data
383 Table 871. RUN_SW_LANE_MARGINING Operation Metadata
384 Table 872. RUN_SW_LANE_MARGINING Completion Data
385 Table 873. READ_SW_ MARGIN_ERR Completion Metadata
386 9 USB3 Tunneling
387 9.1 USB3 Adapter Layer
9.1.1 Encapsulation
388 Table 91. PDF Values for USB3 Tunneling Packets
Table 92. LFPS Tunneled Packet Payload
389 Figure 91. LFPS Tunneled Packet Format
392 Figure 92. Ordered Set Tunneled Packet Format
Table 93. Ordered Set Tunneled Packet Payload
393 Figure 93. Link Command Tunneled Packet Format
394 Figure 94. Tunneled ITP Packet Format
395 Figure 95. Structure of an Unsegmented USB3 Data Packet
396 Figure 96. Segmentation of a USB3 Data Packet
397 9.1.2 Bandwidth Negotiation
398 Figure 97. Bandwidth Negotiation by the Internal Host Controller
399 9.1.3 Timing Parameters
9.2 Internal USB3 Device
Figure 98. Bandwidth Negotiation by the Connection Manager
Table 94. USB3 Adapter Timing Parameters
400 9.2.1 Link Layer
Table 95. USB3 Timers and Timeout Values
401 9.2.2 USB3 Protocol Layer
9.2.3 Descriptors
9.3 Paths
9.3.1 Path Setup
9.3.2 Path Teardown
403 10 DisplayPort™ Tunneling
10.1 DP Adapter Protocol Stack
404 10.1.1 Transport Layer
10.1.2 Protocol Adapter Layer
10.1.3 DP Physical Layer
10.2 DP Adapter States
Figure 101. DP Adapter Protocol Stack Layers
405 10.2.1 Reset
10.2.2 Present
Figure 102. DP Adapter State Machine
406 10.2.3 Plugged
10.2.4 Paired
10.3 Interfaces
10.3.1 DisplayPort
407 Table 101. DisplayPort Modes Of Operation Over DisplayPort Tunneling
408 10.3.2 Programming Model
Figure 103. DP Adapter Path Directions
Table 102. Recommended Path Parameters
409 10.3.3 Hot Plug and Hot Removal Events
410 Figure 104. DP Stream Resource Mapping Examples
Table 103. DP Stream Resource Allocation Commands
411 10.3.4 DisplayPort Over USB4 Fabric
Table 104. AUX Path Tunneled Packet Types
Table 105. Main-Link Path Tunneled Packet Types
412 Figure 105. AUX Channel Framing
Figure 106. AUX Packet Format
413 Figure 107. AUX Packet Example
414 Figure 108. HPD Packet Format
Figure 109. SET_CONFIG Packet Format
416 Table 106. SET_CONFIG Message
418 10.4 System Flows
10.4.1 Connection Manager Discovery
Figure 1010. ACK Packet Format
419 10.4.2 Path Configuration
Figure 1011. Power On to HPD Sequence
421 Table 107. DisplayPort Required Bandwidth (Gbps)
422 10.4.3 HPD Event Propagation
423 10.4.4 AUX Request and Response Handling
Table 108. HPD Event Propagation Delay Requirement
424 Figure 1012. Target AUX Transaction Flow
425 Figure 1013. Snoop AUX Transaction Flow
426 Table 109. DPCD Internal Addresses
427 Figure 1014. DP IN Adapter AUX Handling State Machine
Table 1010. DP IN Adapter AUX Handling State Machine
430 Figure 1015. AUX Timing
Table 1011. AUX Delay Requirements
Table 1012. Aggregated DisplayPort Capabilities
432 10.4.5 DP Adapters Init Flow
10.4.6 Source Discovery
Figure 1016. Example DP Source Discovery Sequence
433 Table 1013. DP Adapter Operation Mode Transitions
434 10.4.7 Down-Spread Control
10.4.8 Stream Mode Set
10.4.9 DSC and FEC Enable
435 10.4.10 DP Link Training
437 Figure 1017. DP Link Training – LTTPR CR_DONE
438 Figure 1018. DP Link Training – LTTPR – EQ Phase
439 Figure 1019. DP Link Training – DPRX – CR_DONE Phase
440 Figure 1020. DP Link Training – DPRX – EQ Phase
442 10.4.11 Power States Set
10.4.12 DP Main-Link Disable
443 10.4.13 Link-Init
10.4.14 DP PHY Testability
444 10.5 High Speed Tunneling
445 10.5.1 SST Tunneling
Figure 1021. Main-Link SST Stream to Tunneled Packets
446 Figure 1022. TU Set Packing for a 4-Lane Main-Link
447 Figure 1023. TU Set Packing for a 2-Lane Main-Link
448 Figure 1024. TU Set Packing for a 1-Lane Main-Link
449 Figure 1025. EOC Symbol Packing Example
Figure 1026. TU Set Header Format
451 Figure 1027. Video Data Packet Format
Figure 1028. MSA Header Format
452 Figure 1029. MSA Packet Format
453 Figure 1030. Blank Start Header Format
454 Figure 1031. Blank Start Packet Format
Table 1014. Blank Start Control Link Symbols Mapping
455 Figure 1032. Secondary TU Header Format
457 Figure 1033. Tunneled Secondary Data Path Format
458 Figure 1034. Secondary Data to Secondary TUs Examples
459 Table 1015. Fill Count Prev_Factor
460 Figure 1035. Non-Secondary Data Packet Fill Count Examples
461 10.5.2 MST Tunneling
Figure 1036. Secondary Data Packet Fill Count Examples
462 Figure 1037. Sub-MTP TU Structures
Figure 1038. Sub-MTP TU Header Format
Table 1016. Slot Zero Sub-MTP TU Header Types
463 Table 1017. Non-Slot Zero Sub-MTP TU Header Types
Table 1018. Slot Zero Sub-MTP TU Packet Rules
464 Table 1019. Non- Zero Slot Sub-MTP TU Packet Rules
465 Table 1020. K-Code Index Nibble in Parameter Byte
466 Figure 1039. Sub-MTP TU 4-Lane Mapping
Figure 1040. Sub-MTP TU 2-Lane Mapping
467 Figure 1041. Sub-MTP TU 1-Lane Mapping
Figure 1042. Unallocated Sequence, 1-Lane
468 Figure 1043. Shifting SR, 1-Lane
Figure 1044. ACT Sequence, 1-Lane
469 Figure 1045. SF and VCPF Sequence 4-Lane
470 10.5.3 FEC
Figure 1046. MST Packet Format
472 10.5.4 DP OUT Adapter Buffer
Figure 1047. FEC_DECODE Packet Format
Figure 1048. FEC Command Format
473 Figure 1049. Active Video to Blanking
474 10.5.5 HDCP
10.6 DP Link Clock Sync
475 10.6.1 Synchronization Method
Figure 1050: Adjust PLL Event Occurrence
476 Figure 1051. Lifetime Counter Format
477 Figure 1052. Filtered Lifetime Counter Logic Concept
Table 1021. FLC Calculation Examples
478 Figure 1053. DP Clock Sync Packet Format
479 10.6.2 DP Adapter Requirements
Figure 1054. DP Clock Sync Packet Example
480 10.7 DP BW Allocation Mode
10.7.1 DP BW Allocation Mode Enablement
481 10.7.2 Interaction with DPTX
Table 1022. DPCD Bandwidth Allocation Registers
482 Table 1023. DP IN Adapter Configuration Space Mapping
483 Figure 1055: DP IN Adapter Interaction with DPTX During DP BW Allocation
484 10.7.3 Interaction with the Connection Manager
485 Figure 1056: DP BW Allocation Interaction with Connection Manager
486 10.8 Timing Parameters
487 11 PCI Express Tunneling
488 11.1 PCIe Adapter Layer
11.1.1 Encapsulation
Table 111. PDF Values for PCIe Tunneled Packets
489 Figure 111. Tunneled PCIe TLP
490 Figure 112. Tunneled PTM Example
Table 112. TLP Pre-Header
491 Figure 113. Tunneled PCIe DLLP
492 Figure 114. PCIe DLLP and TLP Tunneled Packet Payload
493 Table 113. TS Ordered Sets
Table 114. Electrical Idle Ordered Sets
495 11.1.2 USB4 Hot-Plug
11.2 Internal PCIe Ports
11.2.1 PCIe Physical Layer Logical Sub-block
496 11.2.2 PCIe Data Link Layer
11.2.3 PCIe Transaction Layer
497 11.2.4 PCIe Link Timers (Informative)
498 11.2.5 Precision Time Measurement (PTM) Mechanism
Table 115. PCIe Link Timer Ranges
499 Figure 115: Example of PTM Relationships
500 Figure 116: PTM ResponseD Message
502 Figure 117: TMU to PTM Parameters Illustration
503 11.2.6 Timing Parameters
11.3 Paths
11.3.1 Path Set-Up
11.3.2 Path Tear-Down
Table 116. PCIe Adapter Timing Parameters
504 12 Host Interface
505 12.1 Descriptor Ring Mode
12.1.1 DW, Byte, and Bit Order
506 12.1.2 Raw Mode
12.1.3 Frame Mode
507 Figure 121. Segmentation of a Frame
Table 121. Frame Mode Tunneled Packet Format
508 12.2 End-to-End (E2E) Flow Control
12.2.1 E2E Flow Control Packets
509 Figure 122. Example of Forwarding an E2E Credit Grant Packet
Figure 123. E2E Credit Grant / Sync Packet Format
Table 122. E2E Credit Grant Packet Header
Table 123. E2E Credit Grant Packet Payload
510 12.2.2 Flow Control Rules
Table 124. E2E Credit Sync Packet Header
Table 125. E2E Credit Sync Packet Payload
513 12.3 Transmit Interface
12.3.1 Transmit Descriptor Structure
Figure 124. Transmit Descriptor Structure
Table 126. Transmit Descriptor Contents
514 12.3.2 Transmit Flow
516 12.4 Receive Interface
12.4.1 Receive Descriptor Structure
Figure 125. Receive Descriptor Structure (Posted by Host)
Table 127. Receive Descriptor Contents (Posted by Host)
517 Figure 126. Receive Descriptor Structure (Posted by Host Interface Adapter Layer)
Table 128. Receive Descriptor Contents (Posted by Host Interface Adapter Layer)
518 12.4.2 Receive Flow
520 12.5 Interrupts
12.5.1 Interrupt Causes
12.5.2 Interrupt Masks
12.5.3 Interrupt Vectors
12.5.4 Interrupt Moderation
521 12.6 Programming Interface
Figure 127. Interrupt Moderation
522 12.6.1 Access Types
12.6.2 Registers Summary
Table 129. Access Types
Table 1210. Summary of Memory BAR Registers
523 12.6.3 Registers Description
Table 1211. Host Interface Capabilities Register
524 Table 1212. Host Interface Reset Register
Table 1213. Host Interface Control Register
Table 1214. Host Interface CL1 Enable
Table 1215. Host Interface CL2 Enable
525 Table 1216. Base Address Low Register
Table 1217. Base Address High Register
Table 1218. Producer and Consumer Indexes Register
526 Table 1219. Ring Size Register
527 Table 1220. Ring Control Register
Table 1221. Base Address Low Register
Table 1222. Base Address High Register
528 Table 1223. Producer and Consumer Indexes Register
Table 1224. Ring Size Register
529 Table 1225. Ring Control Register
530 Figure 128. Structure of the Interrupt Status Registers
Table 1226. PDF Bit Masks Register
531 Table 1227. Interrupt Status
Table 1228. Interrupt Status Clear
Table 1229. Interrupt Status Set
532 Table 1230. Interrupt Mask
Table 1231. Interrupt Mask Clear
Table 1232. Interrupt Mask Set
Table 1233. Interrupt Throttling Rate (ITR)
533 Figure 129. Structure of the Interrupt Vector Allocation Registers (IVAR)
Table 1234. Interrupt Vector Allocation (IVAR)
534 Figure 1210. Structure of the Receive Ring Vacancy Control Register
Table 1235. Receive Ring Vacancy Control
Table 1236. Receive Ring Vacancy Status
535 12.7 Timing Parameters
13 Interoperability with Thunderbolt™ 3 (TBT3) Systems
13.1 Electrical Layer
Table 1237. Host Interface Timing Parameters
Table 131. Thunderbolt 3 Parameters
536 13.2 Logical Layer
13.2.1 Sideband Channel
Figure 131. Bidirectional Re-timer Topology
537 Table 132. TBT3 LT Transaction Types
Table 133. STX Symbol
538 Figure 132. Bounce Mechanism
Table 134. Contents of Byte 2 in a Broadcast RT Transaction
539 Table 135. SB Registers
Table 136. SB Registers Fields
540 Table 137. Lane Attributes
544 13.2.2 Logical Layer State Machine
545 13.2.3 USB4 Link Operation
13.2.4 Sleep and Wake
Table 138. TS1 and TS2 Ordered Set Structure
546 Table 139. Router State Retained During Sleep
547 13.2.5 Timing Parameters
13.3 Transport Layer
13.3.1 Adapter Numbering Rules
13.3.2 Maximum HopID
13.3.3 Connectivity Rules
Table 1310. Logical Layer Timing Parameters
548 13.3.4 Buffer Allocation
13.4 Configuration Layer
13.4.1 Router Enumeration
13.4.2 Notification Packet
13.4.3 Bit Banging Interface
Table 1311. Buffer Allocation by TBT3 Connection Manager
549 13.4.4 Control Packet Routing
550 13.5 Time Synchronization
13.6 Configuration Spaces
551 13.6.1 Router Configuration Space
Figure 133. Structure of the Vendor Specific 1 Capability
Table 1312. Configuration Register Fields Access Types
Table 1313. List of TBT3-Compatible Router Configuration Capabilities
552 Table 1314. Vendor Specific 1 Capability Fields
556 Figure 134. Structure of the Vendor Specific 3 Capability
Table 1315. Vendor Specific 3 Capability Fields
558 Figure 135. Structure of the Vendor Specific 4 Capability
Table 1316. Vendor Specific 4 Capability Fields
559 Figure 136. Structure of the Vendor Specific Extended 6 Capability
560 Figure 137. Example Vendor Specific Extended 6 Capability
Figure 138. Structure of the Common Region
Table 1317. Common Region Fields
562 Figure 139. Structure of a USB4 Port Region
Table 1318. USB4 Port Region Fields
566 13.6.2 Adapter Configuration Space
Table 1319. Adapter Configuration Space Basic Attributes
567 13.7 PCI Express Tunneling
13.7.1 PCIe Power Management
Table 1320. USB4 Port Capability Fields
568 13.8 DisplayPort Tunneling
13.8.1 AUX Handling
569 13.8.2 IRQ Handling
13.8.3 Connection Manager Discovery
570 13.8.4 Sink Count Read
13.8.5 Power States Set
13.8.6 DisplayPort Link Training
571 Figure 1310. DP IN Adapter Link Training State Machine
Table 1321. DP IN Adapter Link Training State Machine Transition Table
572 Figure 1311. DP OUT Adapter Link Training State Machine
Table 1322. DP OUT Adapter Link Training State Machine Transition Table
573 13.9 USB3 Functionality
574 Figure 1312. Example of a USB4-Based Dock with an Internal Host Controller
575 13.10 Host-to-Host Tunneling
A Verification of CRC, Scrambling, and FEC Calculations
A.1 Transport Layer Packet HEC
A.2 Control Packet CRC
Figure A1. Examples of Transport Layer Packet HEC Calculation
576 A.3 Sideband Channel AT Transaction CRC
Table A1. Examples of Control Packet CRC Calculation
Table A2. Example of a Read Command
Table A3. Example of a Write Command
577 A.4 Scrambler
A.5 Logical Layer RS-FEC
Table A4. Examples of Scrambler Computations
Table A5. Example 1 – RS-FEC Block
579 Table A6. Example 2 – RS-FEC Block
580 Table A7. Example 3 – RS-FEC Block
581 Table A8. Example 4 – RS-FEC Block
582 A.6 USB3 Tunneling CRC
583 A.7 Host Interface Frame CRC
Figure A2. Examples of USB3 Tunneling Calculations
588 A.8 ECC Examples
Figure A3. Example of a Credit Grant Record
Figure A4. Example of an HPD Packet Payload
Figure A5. Example of a SET_CONFIG Packet Payload
589 B Summary of Transport Layer Packets
Figure A6. Example of TU Set Header
Figure A7. Example of a Sub-MTP TU Header
Figure A8. Example of an E2E Credit Sync Packet Payload
Table B1. Transport Layer Packet Summary
590 C Examples of Link Power Management Flows
C.1 Entry to Low Power States
C.1.1 Successful Entry to CL2 State
591 C.1.2 Successful Entry to CL0s State
Figure C1. Successful Entry to CL2 State
Figure C2. Successful Entry to CL0s State
592 C.1.3 Rejection to Enter CL2 State
C.1.4 Concurrent Requests to Enter Low Power State
Figure C3. Failure to Enter CL2 State
593 C.1.5 CL2_REQ Ordered Sets are Not Received
Figure C4. Concurrent Requests to Enter CL2 State
594 C.1.6 CL2_REQ Ordered Sets are Partially Received
Figure C5. Error in CL2_REQ Ordered Sets
Figure C6. CL2_REQ Ordered Sets are Partially Received
595 C.1.7 Error in CL2_ACK Ordered Sets
Figure C7. Errors in CL2_REQ Reception and CL_NACK Response
596 C.1.8 Error in CL_OFF Ordered Sets
Figure C8. Error in CL2_ACK Ordered Sets
Figure C9. Error in CL_OFF Ordered Sets
597 C.2 Exit from Low Power States
C.2.1 Example: Exit from CL0s State
598 Figure C10. CL0s Exit
599 C.2.2 Example: Exit from CL2 (or CL1) State
600 Figure C11. CL2 (or CL1) Exit
601 D Serial Time Link Protocol (STLP)
D.1 Time Synchronization
602 D.2 Serial Time Link Packet Format
Figure D1. Pulse Width Modulation
Figure D2. Serial Time Link Packet Structure
603 Figure D3. Serial Time Link Packet Format
Table D1. Serial Time Link Packet Fields
604 Figure D4. TMU_CLK_OUT and TMU_CLK_IN Parameters
605 D.3 TMU_CLK_OUT and TMU_CLK_IN
Figure D5. Definition of TCOJTR
Table D2. TMU_CLK_OUT and TMU_CLK_IN Specifications
606 E Ingress Buffer Space
E.1 Target Bandwidth Buffer Calculation
E.1.1 Example for USB3 Tunneling Ingress Buffer Calculation
607 E.2 Ingress Buffers Calculation for DP Main Path

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