BS IEC 60747-8:2010:2011 Edition
$215.11
Semiconductor devices. Discrete devices – Field-effect transistors
| Published By | Publication Date | Number of Pages |
| BSI | 2011 | 80 |
IEC 60747-8:2010 gives standards for the following categories of field-effect transistors: – type A: junction-gate type; – type B: insulated-gate depletion (normally on) type; – type C: insulated-gate enhancement (normally off) type. The main changes with respect to the previous edition are listed below. a) “Clause 3 Classification” was moved and added to Clause 1. b) “Clause 4 Terminology and letter symbols” was divided into “Clause 3 Terms and definitions” and “Clause 4 Letter symbols” was amended with additions and deletions. c) Clause 5, 6 and 7 were amended with necessary additions and deletions. This publication is to be read in conjunction with /2.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 4 | English CONTENTS |
| 8 | FOREWORD |
| 10 | 1 Scope 2 Normative references |
| 11 | 3 Terms and definitions 3.1 Types of field-effect transistors |
| 12 | 3.2 General terms |
| 14 | 3.3 Terms related to ratings and characteristics |
| 16 | Figures Figure 1 – Basic waveforms to specify the gate charges |
| 18 | Figure 2 – Integral times for the turn-on energy Eon and turn-off energy Eoff |
| 19 | 3.4 Conventional used terms 4 Letter symbols 4.1 General 4.2 Additional general subscripts 4.3 List of letter symbols Tables Table 1 – Terms for MOSFET in this standard and the conventional used terms for the inverse diode integrated in the MOSFET |
| 23 | Figure 3 – Switching times |
| 24 | 5 Essential ratings and characteristics 5.1 General 5.2 Ratings (limiting values) |
| 25 | 5.3 Characteristics |
| 36 | 6 Measuring methods 6.1 General 6.2 Verification of ratings (limiting values) Table 2 – Acceptance defining characteristics |
| 37 | Figure 4 – Circuit diagram for testing of drain-source voltage Figure 5 – Circuit diagram for testing of gate-source voltage |
| 38 | Figure 6 – Circuit diagram for testing of gate-drain voltage |
| 39 | Figure 7 – Basic circuit for the testing of drain current |
| 40 | Figure 8 – Circuit diagram for testing of peak drain current Figure 9 – Basic circuit for the testing of reverse drain current of MOSFETs |
| 41 | Figure 10 – Basic circuit for the testing of peak reverse drain current of MOSFETs |
| 42 | Figure 11 – Circuit diagram for verifying FBSOA |
| 43 | Figure 12 – Circuit diagram for verifying RBSOA Figure 13 – Test waveforms for verifying RBSOA |
| 44 | Figure 14 – Circuit for testing safe operating pulse duration at load short circuit |
| 45 | Figure 15 – Waveforms of gate-source voltage VGS, drain current ID and voltage VDS during load short circuit condition SCSOA |
| 46 | Figure 16 – Circuit for the inductive avalanche switching Figure 17 – Waveforms of ID, VDS and VGS during unclamped inductive switching |
| 47 | Figure 18 – Waveforms of ID, VDS and VGS for the non-repetitive avalanche switching |
| 48 | 6.3 Methods of measurement Figure 19 – Circuit diagrams for the measurement drain-source breakdown voltage |
| 49 | Figure 20 – Circuit diagram for measurement of gate-source off-statevoltage and gate-source threshold voltage |
| 50 | Figure 21 – Circuit diagram for drain leakage (or off-state) current or drain cut-off current measurement |
| 51 | Figure 22 – Circuit diagram for measuring of gate cut-off current or gate leakage current |
| 52 | Figure 23 – Basic circuit of measurement for on-state resistance Figure 24 – On-state resistance |
| 53 | Figure 25 – Circuit diagram for switching time Figure 26 – Schematic switching waveforms and times |
| 54 | Figure 27 – Circuit for determining the turn-on andturn-off power dissipation and/or energy |
| 56 | Figure 28 – Circuit diagrams for the measurement gate charges |
| 57 | Figure 29 – Basic for the measurement of short-circuit input capacitance |
| 58 | Figure 30 – Basic circuit for measurement of short-circuit output capacitance (Coss) |
| 59 | Figure 31 – Circuit for measurement of reverse transfer capacitance Crss |
| 60 | Figure 32 – Circuit for measurement of internal gate resistance |
| 61 | Figure 33 – Circuit diagram for MOSFET forward recovery timeand recovered charge (Method 1) Figure 34 – Current waveform through MOSFET (Method 1) |
| 62 | Figure 35 – Circuit diagram for MOSFET forward recovery timeand recovered charge (Method 2) |
| 63 | Figure 36 – Current waveform through MOSFET (Method 2) |
| 64 | Figure 37 – Circuit diagram for the measurement of drain-source reverse voltage |
| 65 | Figure 38 – Basic circuit for the measurement of the output conductance goss (method 1: null method) |
| 66 | Figure 39 – Basic circuit for the measurement of the output conductance goss (method 2: two-voltmeter method) |
| 67 | Figure 40 – Circuit for the measurement of short-circuitforward transconductance gfs (Method 1: Null method) |
| 68 | Figure 41 – Circuit for the measurement of forward transconductance gfs (method 2: two-voltmeter method) |
| 69 | Figure 42 – Block diagram for the measurement of equivalent input noise voltage Figure 43 – Circuit for the measurement of equivalent input noise voltage |
| 70 | Figure 44 – Circuit diagram for the measurement of on-state drain-source resistance |
| 71 | Figure 45 – Circuit diagram |
| 73 | 7 Acceptance and reliability 7.1 General requirements 7.2 Acceptance-defining characteristics Table 3 – Acceptance-defining characteristics for endurance and reliability tests |
| 74 | 7.3 Endurance and reliability tests Figure 46 – Circuit for high-temperature blockings Figure 47 – Circuit for high-temperature gate bias |
| 75 | 7.4 Type tests and routine tests Figure 48 – Circuit for intermittent operating life |
| 76 | Table 4 – Minimum type and routine tests for FETs when applicable |
| 77 | Bibliography |
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