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BS IEC 62014-4:2015

BS IEC 62014-4:2015

$215.11

IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows

Published By Publication Date Number of Pages
BSI 2015 380
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This standard describes an eXtensible Markup Language (XML) schema1 for meta-data documenting intellectual property (IP) used in the development, implementation, and verification of electronic systems and an application programming interface (API) to provide tool access to the meta-data. This schema provides a standard method to document IP that is compatible with automated integration techniques.The API provides a standard method for linking tools into a system development framework, enabling a more flexible, optimized development environment. Tools compliant with this standard will be able to interpret, configure, integrate, and manipulate IP blocks that comply with the IP meta-data description. The standard is based on version 1.4 IP-XACT of The SPIRIT Consortium. The standard is independent of any specific design processes. It does not cover those behavioral characteristics of the IP that are not relevant to integration.

PDF Catalog

PDF Pages PDF Title
4 Contents
12 Introduction
15 1.2 Purpose
1.3 Design environment
19 1.4 IP-XACT Enabled implementations
20 1.5 Conventions used
25 1.6 Use of color in this standard
1.7 Contents of this standard
26 2. Normative references
28 3. Definitions, acronyms, and abbreviations
3.1 Definitions
34 3.2 Acronyms and abbreviations
36 4. Interoperability use model
4.1 Roles and responsibilities
37 4.2 IP-XACT IP exchange flows
40 5. Interface definition descriptions
5.1 Definition descriptions
5.2 Bus definition
43 5.3 Abstraction definition
44 5.4 Ports
45 5.5 Wire ports
47 5.6 Qualifiers
49 5.7 Wire port group
51 5.8 Wire port mode constraints
52 5.9 Wire port mirrored-mode constraints
54 5.10 Transactional ports
56 5.11 Transactional port group
57 5.12 Extending bus and abstraction definitions
60 5.13 Clock and reset handling
62 6. Component descriptions
6.1 Component
65 6.2 Interfaces
6.3 Interface interconnections
67 6.4 Complex interface interconnections
69 6.5 Bus interfaces
80 6.6 Component channels
82 6.7 Address spaces
94 6.8 Memory maps
110 6.9 Remapping
115 6.10 Registers
133 6.11 Models
164 6.12 Component generators
166 6.13 File sets
178 6.14 Choices
180 6.15 White box elements
181 6.16 White box element reference
183 6.17 CPUs
184 7. Design descriptions
7.1 Design
186 7.2 Design component instances
188 7.3 Design interconnections
189 7.4 Active, monitored, and monitor interfaces
191 7.5 Design ad hoc connections
193 7.6 Design hierarchical connections
196 8. Abstractor descriptions
8.1 Abstractor
198 8.2 Abstractor interfaces
200 8.3 Abstractor models
202 8.4 Abstractor views
204 8.5 Abstractor ports
206 8.6 Abstractor wire ports
208 8.7 Abstractor generators
212 9. Generator chain descriptions
9.1 generatorChain
214 9.2 generatorChainSelector
215 9.3 generatorChain component selector
216 9.4 generatorChain generator
220 10. Design configuration descriptions
10.1 Design configuration
10.2 designConfiguration
222 10.3 generatorChainConfiguration
224 10.4 interconnectionConfiguration
226 11. Addressing and data visibility
11.1 Calculating the bit address of a bit in a memory map
227 11.2 Calculating the bus address at the slave bus interface
11.3 Address modifications of an interconnection
228 11.4 Address modifications of a channel
229 11.5 Addressing in the master
11.6 Visibility of bits
231 11.7 Address translation in a bridge
232 Annex A (informative) Bibliography
234 Annex B (normative) Semantic consistency rules
258 Annex C (normative) Common elements and concepts
276 Annex D (normative) Types
280 Annex E (normative) Dependency XPATH
284 Annex F (informative) External bus with an internal/digital interface
286 Annex G (normative) Tight generator interface
364 Annex H (informative) Bridges and channels
374 Annex I (informative) IEEE List of Participants

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BS IEC 62014-4:2015
$215.11