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BS IEC 62530-2:2023

BS IEC 62530-2:2023

$215.11

System Verilog – Universal Verification Methodology Language Reference Manual

Published By Publication Date Number of Pages
BSI 2023 462
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PDF Pages PDF Title
2 undefined
4 Contents
15 Introduction
16 1. Overview
1.1 Scope
1.2 Purpose
1.3 Word usage
17 1.4 Conventions used
1.4.1 Visual cues (meta-syntax)
1.4.2 Return values
1.4.3 Inheritance
18 1.4.4 Operation order on equivalent data objects
1.4.5 uvm_pkg
1.4.6 Random stability
19 2. Normative references
3. Definitions, acronyms, and abbreviations
3.1 Definitions
20 3.2 Acronyms and abbreviations
21 4. Universal Verification Methodology (UVM) class reference
22 5. Base classes
5.1 Overview
5.2 uvm_void
23 5.3 uvm_object
5.3.1 Class declaration
5.3.2 Common methods
5.3.3 Seeding
5.3.4 Identification
25 5.3.5 Creation
5.3.6 Printing
26 5.3.7 Recording
27 5.3.8 Copying
5.3.9 Comparing
28 5.3.10 Packing
29 5.3.11 Unpacking
30 5.3.12 Configuration
5.3.13 Field operations
5.3.14 Active policy
31 5.4 uvm_transaction
5.4.1 Class declaration
5.4.2 Methods
35 5.5 uvm_port_base #(IF)
5.5.1 Class declaration
5.5.2 Methods
38 5.6 uvm_time
5.6.1 Class declaration
5.6.2 Common methods
40 5.7 uvm_field_op
5.7.1 Class declaration
5.7.2 Methods
42 6. Reporting classes
6.1 Overview
43 6.2 uvm_report_message
6.2.1 Class declaration
6.2.2 Common methods
6.2.3 Infrastructure references
44 6.2.4 Message fields
45 6.3 uvm_report_object
46 6.3.1 Class declaration
6.3.2 Common methods
6.3.3 Reporting
48 6.3.4 Verbosity configuration
49 6.3.5 Action configuration
50 6.3.6 File configuration
6.3.7 Override configuration
51 6.3.8 Report handler configuration
6.4 uvm_report_handler
6.4.1 Class declaration
6.4.2 Common methods
6.4.3 Verbosity configuration
52 6.4.4 Action configuration
53 6.4.5 File configuration
6.4.6 Override configuration
54 6.4.7 Message processing
6.5 Report server
6.5.1 uvm_report_server
57 6.5.2 uvm_default_report_server
6.6 uvm_report_catcher
58 6.6.1 Class declaration
6.6.2 Common methods
6.6.3 Current message state
60 6.6.4 Change message state
6.6.5 Callback interface
61 6.6.6 Reporting
62 7. Recording classes
63 7.1 uvm_tr_database
7.1.1 Class declaration
7.1.2 Common methods
7.1.3 Database API
7.1.4 Stream API
64 7.1.5 Link API
7.1.6 Implementation agnostic API
65 7.2 uvm_tr_stream
7.2.1 Class declaration
7.2.2 Common methods
7.2.3 Introspection API
66 7.2.4 Stream API
67 7.2.5 Transaction recorder API
7.2.6 Handles
68 7.2.7 Implementation agnostic API
69 7.3 UVM links
7.3.1 uvm_link_base
70 7.3.2 uvm_parent_child_link
71 7.3.3 uvm_cause_effect_link
72 7.3.4 uvm_related_link
73 8. Factory classes
8.1 Overview
8.2 Factory component and object wrappers
8.2.1 Introduction
8.2.2 type_id
74 8.2.3 uvm_component_registry #(T,Tname)
75 8.2.4 uvm_object_registry #(T,Tname)
77 8.2.5 Abstract registries
79 8.3 UVM factory
8.3.1 uvm_factory
84 8.3.2 uvm_object_wrapper
85 8.3.3 uvm_default_factory
9. Phasing
9.1 Overview
9.2 Implementation
9.2.1 Class hierarchy
9.2.2 Phasing related classes
86 9.2.3 Common and run-time phases
9.3 Phasing definition classes
9.3.1 uvm_phase
94 9.3.2 uvm_phase_state_change
9.3.3 uvm_phase_cb
95 9.4 uvm_domain
9.4.1 Class declaration
9.4.2 Methods
96 9.5 uvm_bottomup_phase
9.5.1 Class declaration
9.5.2 Methods
9.6 uvm_task_phase
97 9.6.1 Class declaration
9.6.2 Methods
9.7 uvm_topdown_phase
98 9.7.1 Class declaration
9.7.2 Methods
9.8 Predefined phases
99 9.8.1 Common phases
100 9.8.2 UVM run-time phases
102 10. Synchronization classes
10.1 Event classes
10.1.1 uvm_event_base
104 10.1.2 uvm_event#(t)
105 10.2 uvm_event_callback
10.2.1 Class declaration
10.2.2 Methods
106 10.3 uvm_barrier
10.3.1 Class declaration
10.3.2 Methods
108 10.4 Pool classes
10.4.1 uvm_event_pool
10.4.2 uvm_barrier_pool
109 10.5 Objection mechanism
10.5.1 uvm_objection
113 10.5.2 uvm_objection_callback
114 10.6 uvm_heartbeat
10.6.1 Class declaration
10.6.2 Methods
116 10.7 Callbacks classes
10.7.1 uvm_callback
10.7.2 uvm_callbacks #(T,CB)
119 11. Container classes
11.1 Overview
120 11.2 uvm_pool #(KEY,T)
11.2.1 Class declaration
11.2.2 Methods
122 11.3 uvm_queue #(T)
11.3.1 Class declaration
11.3.2 Methods
124 12. UVM TLM interfaces
12.1 Overview
12.2 UVM TLM 1
12.2.1 General
125 12.2.2 Unidirectional interfaces and ports
12.2.3 Bidirectional interfaces and ports
126 12.2.4 uvm_tlm_if_base #(T1,T2)
129 12.2.5 Port classes
130 12.2.6 Export classes
132 12.2.7 Implementation (imp) classes
134 12.2.8 FIFO classes
137 12.2.9 Channel classes
140 12.2.10 Analysis ports
142 12.3 UVM TLM 2
12.3.1 General
12.3.2 uvm_tlm_if: transport interfaces
144 12.3.3 Enumerations
12.3.4 Generic payload and extensions
155 12.3.5 Sockets
161 12.3.6 Port classes
162 12.3.7 Export classes
12.3.8 Implementation (imp) classes imps
163 12.3.9 uvm_tlm_time
13. Predefined component classes
13.1 uvm_component
164 13.1.1 Class declaration
13.1.2 Common methods
165 13.1.3 Hierarchy interface
166 13.1.4 Phasing interface
171 13.1.5 Configuration interface
13.1.6 Objection interface
172 13.1.7 Recording interface
176 13.1.8 Other interfaces
13.2 uvm_test
13.2.1 Class declaration
13.2.2 Methods
177 13.3 uvm_env
13.3.1 Class declaration
13.3.2 Methods
13.4 uvm_agent
13.4.1 Class declaration
13.4.2 Methods
178 13.5 uvm_monitor
13.5.1 Class declaration
13.5.2 Methods
13.6 uvm_scoreboard
13.6.1 Class declaration
13.6.2 Methods
179 13.7 uvm_driver #(REQ,RSP)
13.7.1 Class declaration
13.7.2 Ports
13.7.3 Methods
13.8 uvm_push_driver #(REQ,RSP)
180 13.8.1 Class declaration
13.8.2 Ports
13.8.3 Methods
13.9 uvm_subscriber
13.9.1 Class declaration
13.9.2 Ports
181 13.9.3 Methods
14. Sequence classes
14.1 uvm_sequence_item
14.1.1 Class declaration
14.1.2 Common fields
183 14.1.3 Reporting interface
185 14.2 uvm_sequence_base
14.2.1 Class declaration
14.2.2 Common methods
186 14.2.3 Sequence execution
187 14.2.4 Run-time phasing
188 14.2.5 Sequence control
190 14.2.6 Sequence item execution
192 14.2.7 Response API
193 14.3 uvm_sequence #(REQ,RSP)
14.3.1 Class declaration
194 14.3.2 Variables
14.3.3 Methods
195 14.4 uvm_sequence_library
14.4.1 Class declaration
14.4.2 Example
14.4.3 Common methods
196 14.4.4 Sequence selection
197 14.4.5 Sequence registration
198 15. Sequencer classes
15.1 Overview
15.1.1 Sequencer variants
15.1.2 Sequence item ports
199 15.2 Sequencer interface
15.2.1 uvm_sqr_if_base #(T1,T2)
201 15.2.2 Sequence item pull ports
15.3 uvm_sequencer_base
15.3.1 Class declaration
202 15.3.2 Methods
206 15.3.3 Requests
15.3.4 Responses
15.3.5 Default sequence
207 15.4 Common sequencer API
15.4.1 Method
208 15.4.2 Request
15.4.3 Responses
15.5 uvm_sequencer #(REQ,RSP)
15.5.1 Class declaration
15.5.2 Methods
211 15.6 uvm_push_sequencer #(REQ,RSP)
15.6.1 Class declaration
15.6.2 Ports
15.6.3 Methods
212 16. Policy classes
16.1 uvm_policy
213 16.1.1 Class declaration
16.1.2 Methods
214 16.1.3 Active object
16.1.4 recursion_state_e
215 16.2 uvm_printer
16.2.1 Class declaration
16.2.2 Methods
16.2.3 Methods for printer usage
220 16.2.4 Methods for printer subtyping
16.2.5 Methods for printer configuration
223 16.2.6 Methods for object print control
224 16.2.7 Element stack
225 16.2.8 uvm_printer_element
226 16.2.9 uvm_printer_element_proxy
227 16.2.10 uvm_table_printer
228 16.2.11 uvm_tree_printer
229 16.2.12 uvm_line_printer
230 16.3 uvm_comparer
16.3.1 Class declaration
16.3.2 Methods
231 16.3.3 Methods for comparer usage
234 16.3.4 Methods for comparer configuration
16.3.5 Methods for comparer reporting control
235 16.3.6 Methods for object compare control
16.4 uvm_recorder
16.4.1 Class declaration
236 16.4.2 Methods for recorder configuration
16.4.3 Introspection API
237 16.4.4 Transaction recorder API
238 16.4.5 Handles
16.4.6 Attribute recording
241 16.4.7 Implementation agnostic API
244 16.5 uvm_packer
16.5.1 Class declaration
16.5.2 Methods
245 16.5.3 Methods for packer subtyping
16.5.4 Packing and unpacking
249 16.6 uvm_copier
16.6.1 Class declaration
16.6.2 Methods
250 16.6.3 Methods for object copy control
16.6.4 Methods for copier usage
251 17. Register layer
17.1 Overview
17.2 Global declarations
17.2.1 Types
252 17.2.2 Enumerations
254 17.2.3 uvm_hdl_path_concat
255 18. Register model
18.1 uvm_reg_block
18.1.1 Class declaration
18.1.2 Methods
258 18.1.3 Introspection
261 18.1.4 Coverage
263 18.1.5 Access
265 18.1.6 Back door
267 18.2 uvm_reg_map
18.2.1 Class declaration
268 18.2.2 Common methods
18.2.3 Methods
271 18.2.4 Introspection
274 18.2.5 Bus access
275 18.3 uvm_reg_file
18.3.1 Class declaration
18.3.2 Methods
276 18.3.3 Introspection
18.3.4 Back door
277 18.4 uvm_reg
18.4.1 Class declaration
278 18.4.2 Methods
279 18.4.3 Introspection
281 18.4.4 Access
288 18.4.5 Front door
18.4.6 Back door
291 18.4.7 Coverage
293 18.4.8 Callbacks
294 18.5 uvm_reg_field
18.5.1 Class declaration
18.5.2 Member variables
295 18.5.3 Methods
18.5.4 Introspection
298 18.5.5 Access
304 18.5.6 Callbacks
305 18.6 uvm_mem
18.6.1 Class declaration
306 18.6.2 Variables
18.6.3 Methods
307 18.6.4 Introspection
310 18.6.5 HDL access
313 18.6.6 Front door
314 18.6.7 Back door
316 18.6.8 Coverage
318 18.6.9 Callbacks
319 18.7 uvm_reg_indirect_data
18.7.1 Class declaration
18.7.2 Methods
18.8 uvm_reg_fifo
320 18.8.1 Class declaration
18.8.2 Common variables
18.8.3 Methods
18.8.4 Introspection
321 18.8.5 Access
323 18.9 uvm_vreg
18.9.1 Class declaration
331 18.9.2 uvm_vreg_cbs
332 18.10 uvm_vreg_field
333 18.10.1 Class declaration
18.10.2 Methods
18.10.3 Introspection
334 18.10.4 HDL access
335 18.10.5 Callbacks
337 18.10.6 uvm_vreg_field_cbs
338 18.11 uvm_reg_cbs
18.11.1 Class declaration
18.11.2 Methods
341 18.11.3 Types
18.11.4 uvm_reg_read_only_cbs
342 18.11.5 uvm_reg_write_only_cbs
343 18.12 uvm_mem_mam
18.12.1 Class declaration
18.12.2 Types
18.12.3 Variables
344 18.12.4 Methods
18.12.5 Memory management
345 18.12.6 Introspection
346 18.12.7 uvm_mem_region
349 18.12.8 uvm_mem_mam_policy
350 18.12.9 uvm_mem_mam_cfg
351 19. Register layer interaction with the design
19.1 Generic register operation descriptors
19.1.1 uvm_reg_item
354 19.1.2 uvm_reg_bus_op
356 19.2 Classes for adapting between register and bus operations
19.2.1 uvm_reg_adapter
357 19.2.2 uvm_reg_tlm_adapter
19.3 uvm_reg_predictor
358 19.3.1 Class declaration
19.3.2 Variables
359 19.3.3 Methods
19.4 Register sequence classes
19.4.1 uvm_reg_sequence
366 19.4.2 uvm_reg_frontdoor
367 19.5 uvm_reg_backdoor
19.5.1 Class declaration
19.5.2 Methods
369 19.6 UVM HDL backdoor access support routines
19.6.1 Variables
19.6.2 Methods
371 Annex A (informative) Bibliography
372 Annex B (normative) Macros and defines
B.1 Report macros
373 B.2 Utility and field macros for components and objects
388 B.3 Sequence-related macros
389 B.4 Callback macros
391 B.5 UVM TLM implementation port declaration macros
394 B.6 Size defines
395 B.7 UVM version globals
396 Annex C (normative) Configuration and resource classes
C.1 Overview
C.2 Resources
405 C.3 UVM resource database
408 C.4 UVM configuration database
411 Annex D (normative) Convenience classes, interface, and methods
D.1 uvm_callback_iter
412 D.2 Component interfaces
416 D.3 uvm_reg_block access methods
418 D.4 Callback typedefs
420 Annex E (normative) Test sequences
E.1 uvm_reg_hw_reset_seq
E.2 Bit bashing test sequences
422 E.3 Register access test sequences
424 E.4 Shared register and memory access test sequences
426 E.5 Memory access test sequences
427 E.6 Memory walking-ones test sequences
429 E.7 uvm_reg_mem_hdl_paths_seq
E.8 uvm_reg_mem_built_in_seq
431 Annex F (normative) Package scope functionality
F.1 Overview
F.2 Types and enumerations
438 F.3 Methods and types
442 F.4 Core service
446 F.5 Traversal
449 F.6 uvm_run_test_callback
450 F.7 uvm_root
454 Annex G (normative) Command line arguments
G.1 Command line processing
456 G.2 Built-in UVM-aware command line arguments
459 Annex H (normative) Deprecation
H.1 General
H.2 Constructs that have been deprecated

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