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BS IEC 62880-1:2017:2020 Edition

BS IEC 62880-1:2017:2020 Edition

$142.49

Semiconductor devices. Stress migration test standard – Copper stress migration test standard

Published By Publication Date Number of Pages
BSI 2020 28
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This part of IEC 62880 describes a constant temperature (isothermal) aging method for testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditions, the method can be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time.

Dual damascene Cu metallization systems usually have liners, such as tantalum (Ta) or tantalum nitride (TaN) on the bottom and sides of trenches etched into dielectric layers. Hence, for structures in which a single via contacts a wide line below it, a void under the via can cause an open circuit at almost the same time as any percentage resistance shift that would satisfy a failure criterion.

PDF Catalog

PDF Pages PDF Title
2 undefined
4 CONTENTS
5 FOREWORD
7 1 Scope
2 Normative references
3 Terms and definitions
9 4 Test method
4.1 Test structures
10 Figures
Figure 1 – SM test structure sketches
12 Figure 2 – SM test structure sketches – Illustrative sketches ofproposed optional SM test structures
13 4.2 Test equipment
4.3 Test temperatures
4.4 Test conditions, sample size and measurements
4.5 Failure criteria
4.6 Passing criteria
14 5 Data to be reported
15 Annex A (informative) Explanation for stress migration, stress induced voiding – Temperature, geometry dependence
A.1 Stress-induced voids
A.2 Stress temperature
16 A.3 Geometry linewidth dependence of SIV risk
Figure A.1 – Temperature dependent behaviour of SM MTF values of5 µm VIA chains in the range of 125 ºC – 275 ºC
17 Figure A.2 – Power-law relation of MTF vs linewidth
18 A.4 VIA size dependence of SIV risk
Figure A.3 – Median time-to-fail SM data as a function of VIA sizes
Figure A.4 – Hydrostatic stress gradient at near roomtemperatures vs VIA size (area)
19 A.5 SIV under multiple VIAs
A.6 Metal thickness dependence of SIV risk
Figure A.5 – FA images of two VIA case andMTF vs multiple VIA of SM
20 A.7 SM lifetime model
Figure A.6 – Metal thickness versus resistance increase under SM tests
21 A.8 Sensitivity for test structure
Figure A.7 – Stress profile of conventional and VIM VIA chains
22 Figure A.8 – SM data of conventional and VIM VIA chains
23 Annex B (informative) Example of geometry dependence for nose pattern
B.1 General
B.2 Geometry factor
Figure B.1 – Representation of real product interconnect
Figure B.2 – Representation of SM nose pattern
24 Figure B.3 – Failure rate – Body area dependence with nose pattern
25 Bibliography

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BS IEC 62880-1:2017
$142.49