BS IEC 63011-3:2018:2019 Edition
$102.76
Integrated circuits. Three dimensional integrated circuits – Model and measurement conditions of through-silicon via
| Published By | Publication Date | Number of Pages |
| BSI | 2019 | 18 |
IEC 63011-3:2018 specifies a reference model of through-silicon via (TSV) electrical characteristics required for an interface design in three dimensional integrated circuit (3-D IC) to transmit and receive digital data and measurement conditions for resistance and capacitance to specify TSV characteristics in 3-D IC. Power devices, RF devices and micro-electromechanical systems (MEMS) are not in the scope of this document.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 2 | undefined |
| 4 | English CONTENTS |
| 5 | FOREWORD |
| 7 | INTRODUCTION |
| 8 | 1 Scope 2 Normative references Figures Figure 1 – Reference of a multi-chip interconnect system |
| 9 | 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions 3.2 Abbreviated terms 4 Measurement conditions to specify TSV characteristics 4.1 Supply chain and TSV circuit model Figure 2 – 3-D IC Supply chain model |
| 10 | 4.2 Reference model of TSV electrical characteristics Figure 3 – TSV electrical characteristic model |
| 11 | 4.3 Measurement conditions to specify TSV electrical characteristics 4.3.1 General 4.3.2 Resistance measurement Tables Table 1 – Policy for model standardization |
| 12 | 4.3.3 Capacitance measurement Figure 4 – Resistance measurement method Figure 5 – Capacitance measurement method |
| 13 | Figure 6 – Measurement conditions to specify TSV electrical characteristicswhen substrate is not connected to power supply |
| 14 | Annex A (informative)Explanatory note A.1 Purpose of establishment A.2 Reference dimension of the TSV model Table A.1 – Parameters and reference values of the TSV model |
| 15 | A.3 Other considerations for implementation A.3.1 General A.3.2 Keep out zone Figure A.1 – Structure of the TSV model |
| 16 | Figure A.2 – KOZ definition Table A.2 – Parameters affecting KOZ |
