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BS ISO 16845-1:2016

$215.11

Road vehicles. Controller area network (CAN) conformance test plan – Data link layer and physical signalling

Published By Publication Date Number of Pages
BSI 2016 140
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PDF Catalog

PDF Pages PDF Title
9 Foreword
10 Introduction
11 1 Scope
2 Normative references
3 Terms and definitions
13 4 Abbreviated terms
14 5 Global overview
5.1 Scope of test plan
5.2 Architecture of test plan
15 5.3 Organization
5.3.1 General organization
16 5.3.2 Test case organization
17 5.3.3 Hierarchical structure of tests
18 6 LT parameters
6.1 Overview
6.2 Description of parameters
6.2.1 Communication parameters
19 6.2.2 Application parameters
20 6.2.3 Bit rate configuration parameter variation for bit timing tests
7 Test type 1, received frame
7.1 Test class 1, valid frame format
7.1.1 Identifier and number of data test in base format
21 7.1.2 Identifier and number of data test in extended format
22 7.1.3 Reception after arbitration lost
23 7.1.4 Acceptance of non-nominal bit in base format frame
7.1.5 Acceptance of non-nominal bit in extended format frame
24 7.1.6 Protocol exception behaviour on non-nominal bit
25 7.1.7 Minimum time for bus idle after protocol exception handling
7.1.8 DLC greater than 8
26 7.1.9 Absent bus idle — Valid frame reception
7.1.10 Stuff acceptance test in base format frame
27 7.1.11 Stuff acceptance test in extended format frame
28 7.1.12 Message validation
29 7.2 Test class 2, error detection
7.2.1 Bit error in data frame
7.2.2 Stuff error for basic frame
30 7.2.3 Stuff error for extended frame
31 7.2.4 Stuff error for FD frame payload bytes
32 7.2.5 CRC error
33 7.2.6 Combination of CRC error and form error
34 7.2.7 Form error in data frame at “CRC delimiter” bit position
7.2.8 Form error at fixed stuff bit in FD frames
35 7.2.9 Form error in data frame at “ACK delimiter” bit position
7.2.10 Form error in data frame at “EOF”
36 7.2.11 Message non-validation
7.3 Test class 3, error frame management
7.3.1 Error flag longer than 6 bits
37 7.3.2 Data frame starting on the third bit of intermission field
7.3.3 Bit error in error flag
38 7.3.4 Form error in error delimiter
7.4 Test class 4, overload frame management
7.4.1 MAC overload generation during intermission field
39 7.4.2 Last bit of EOF
7.4.3 Eighth bit of an error and overload delimiter
40 7.4.4 Bit error in overload flag
7.4.5 Form error in overload delimiter
41 7.4.6 MAC overload generation during intermission field following an error frame
7.4.7 MAC overload generation during intermission field following an overload frame
42 7.5 Test class 5, passive error state class
7.5.1 Passive error flag completion test 1
43 7.5.2 Data frame acceptance after passive error frame transmission
7.5.3 Acceptance of 7 consecutive dominant bits after passive error flag
44 7.5.4 Passive state unchanged on further errors
7.5.5 Passive error flag completion — Test case 2
45 7.5.6 Form error in passive error delimiter
7.5.7 Transition from active to passive ERROR FLAG
46 7.6 Test class 6, error counter management
7.6.1 REC increment on bit error in active error flag
47 7.6.2 REC increment on bit error in overload flag
7.6.3 REC increment when active error flag is longer than 13 bits
48 7.6.4 REC increment when overload flag is longer than 13 bits
7.6.5 REC increment on bit error in the ACK field
7.6.6 REC increment on form error in CRC delimiter
49 7.6.7 REC increment on form error in ACK delimiter
7.6.8 REC increment on form error in EOF field
50 7.6.9 REC increment on stuff error
51 7.6.10 REC increment on CRC error
7.6.11 REC increment on dominant bit after end of error flag
52 7.6.12 REC increment on form error in error delimiter
7.6.13 REC increment on form error in overload delimiter
53 7.6.14 REC decrement on valid frame reception
7.6.15 REC decrement on valid frame reception during passive state
54 7.6.16 REC non-increment on last bit of EOF field
7.6.17 REC non-increment on 13-bit length overload flag
55 7.6.18 REC non-increment on 13-bit length error flag
7.6.19 REC non-increment on last bit of error delimiter
56 7.6.20 REC non-increment on last bit of overload delimiter
7.6.21 REC non-decrement on transmission
57 7.6.22 REC increment on form error at fixed stuff bit in FD frames
7.6.23 REC non-increment on protocol exception in FD frames
58 7.7 Test class 7, bit timing Classical CAN frame format
7.7.1 Sample point test
59 7.7.2 Hard synchronization on SOF reception
7.7.3 Synchronization when e > 0 and e ≤ SJW(N)
60 7.7.4 Synchronization when e > 0 and e > SJW(N)
7.7.5 Synchronization when e < 0 and |e| ≤ SJW(N)
61 7.7.6 Synchronization when e  SJW(N)
7.7.7 Glitch filtering test on positive phase error
62 7.7.8 Glitch filtering test on negative phase error
63 7.7.9 Glitch filtering test in idle state
64 7.7.10 Non-Synchronization after a dominant sampled bit
65 7.7.11 Synchronization when e < 0 and |e| ≤ SJW(N) at “ACK” bit position
7.8 Test class 8, bit timing CAN FD frame format
7.8.1 Sample point test
68 7.8.2 Hard synchronization on “res” bit
69 7.8.3 Synchronization when e > 0 and e ≤ SJW(D)
71 7.8.4 Synchronization when e > 0 and e > SJW(D)
73 7.8.5 Synchronization when e < 0 and |e| ≤ SJW
75 7.8.6 Synchronization when e  SJW
77 7.8.7 Glitch filtering test on positive phase error
79 7.8.8 Glitch filtering test on negative phase error
81 7.8.9 No synchronization after a dominant sampled bit
83 8 Test type 2, transmitted frame
8.1 Test class 1, valid frame format
8.1.1 Identifier and number of data bytes test in base format
8.1.2 Identifier and number of data bytes test in extended format
84 8.1.3 Arbitration in base format frame
85 8.1.4 Arbitration in extended format frame test
86 8.1.5 Message validation
8.1.6 Stuff bit generation capability in base format frame
87 8.1.7 Stuff bit generation capability in extended frame
88 8.1.8 Transmission on the third bit of intermission field after arbitration lost
89 8.2 Test class 2, error detection
8.2.1 Bit error test in base format frame
90 8.2.2 Bit error in extended format frame
91 8.2.3 Stuff error test in base format frame
8.2.4 Stuff error test in extended frame format
92 8.2.5 Form error test
93 8.2.6 Acknowledgement error
94 8.2.7 Form field tolerance test for FD frame format
8.2.8 Bit error at stuff bit position for FD frame payload bytes
95 8.3 Test class 3, error frame management
8.3.1 Error flag longer than 6 bit
8.3.2 Transmission on the third bit of intermission field after error frame
96 8.3.3 Bit error in error flag
8.3.4 Form error in error delimiter
97 8.4 Test class 4, overload frame management
8.4.1 MAC overload generation in intermission field
98 8.4.2 Eighth bit of an error and overload delimiter
8.4.3 Transmission on the third bit of intermission after overload frame
99 8.4.4 Bit error in overload flag
8.4.5 Form error in overload delimiter
100 8.5 Test class 5, passive error state and bus-off
8.5.1 Acceptance of active error flag overwriting passive error flag
8.5.2 Frame acceptance after passive error frame transmission
101 8.5.3 Acceptance of 7 consecutive dominant bits after passive error flag
102 8.5.4 Reception of a frame during suspend transmission
8.5.5 Transmission of a frame after suspend transmission — Test case 1
103 8.5.6 Transmission of a frame after suspend transmission — Test case 2
8.5.7 Transmission of a frame after suspend transmission — Test case 3
8.5.8 Transmission of a frame without suspend transmission
104 8.5.9 No transmission of a frame between the third bit of intermission field and eighth bit of suspend transmission
8.5.10 Bus-off state
105 8.5.11 Bus-off recovery
106 8.5.12 Completion condition for a passive error flag
8.5.13 Form error in passive error delimiter
107 8.5.14 Maximum recovery time after a corrupted frame
8.5.15 Transition from active to passive ERROR FLAG
108 8.6 Test class 6, error counter management
8.6.1 TEC increment on bit error during active error flag
109 8.6.2 TEC increment on bit error during overload flag
8.6.3 TEC increment when active error flag is followed by dominant bits
110 8.6.4 TEC increment when passive error flag is followed by dominant bits
8.6.5 TEC increment when overload flag is followed by dominant bits
111 8.6.6 TEC increment on bit error in data frame
112 8.6.7 TEC increment on form error in a frame
8.6.8 TEC increment on acknowledgement error
113 8.6.9 TEC increment on form error in error delimiter
8.6.10 TEC increment on form error in overload delimiter
114 8.6.11 TEC decrement on successful frame transmission for TEC < 128
8.6.12 TEC decrement on successful frame transmission for TEC > 127
115 8.6.13 TEC non-increment on 13-bit long overload flag
8.6.14 TEC non-increment on 13-bit long error flag
116 8.6.15 TEC non-increment on form error at last bit of overload delimiter
8.6.16 TEC non-increment on form error at last bit of error delimiter
117 8.6.17 TEC non-increment on acknowledgement error in passive state
8.6.18 TEC increment after acknowledgement error in passive state
118 8.6.19 TEC non-increment on stuff error during arbitration
8.6.20 TEC non-decrement on transmission while arbitration lost
119 8.6.21 TEC non-increment after arbitration lost and error
8.7 Test class 7, bit timing
8.7.1 Sample point test
120 8.7.2 Hard synchronization on SOF reception before sample point
121 8.7.3 Hard synchronization on SOF reception after sample point
8.7.4 Synchronization when e < 0 and |e| ≤ SJW(N)
122 8.7.5 Synchronization for e  SJW(N)
123 8.7.6 Glitch filtering test on negative phase error
8.7.7 Non-synchronization on dominant bit transmission
124 8.7.8 Synchronization before information processing time
8.7.9 Synchronization after sample point while sending a dominant bit
125 8.8 Test class 8, bit timing CAN FD frame format
8.8.1 Sample point test
128 8.8.2 Secondary sample point test
131 8.8.3 No synchronization within data phase bits when e < 0; |e| ≤ SJW(D)
133 8.8.4 Glitch filtering test on negative phase error within FD frame bits
134 8.8.5 No synchronization on dominant bit transmission in FD frames
135 9 Test type 3, bi-directional frame
9.1 Test class 1, valid frame format
9.2 Test class 2, error detection
9.3 Test class 3, active error frame management
9.4 Test class 4, overload frame management
9.5 Test class 5, passive-error state and bus-off
136 9.6 Test class 6, error counter management
9.6.1 REC unaffected when increasing TEC
9.6.2 TEC unaffected when increasing REC
BS ISO 16845-1:2016
$215.11