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BS ISO 21111-6:2021

BS ISO 21111-6:2021

$215.11

Road vehicles. In-vehicle Ethernet – Electrical 100-Mbit/s physical entity requirements and conformance test plan

Published By Publication Date Number of Pages
BSI 2021 134
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This document specifies advanced features of an ISO/IEC/IEEE 8802-3 automotive Ethernet PHY (often also called transceiver), e.g. for diagnostic purposes for automotive Ethernet PHYs.

This document specifies:

  • advanced PHY features;

  • wake-up and sleep features;

  • PHY test suite;

  • PHY control IUT requirements and conformance test plan;

  • PCS test suite;

  • PCS IUT requirements and conformance test plan;

  • PMA test suite; and

  • PMA IUT requirements and conformance test plan.

PDF Catalog

PDF Pages PDF Title
2 undefined
7 Foreword
8 Introduction
10 1 Scope
2 Normative references
3 Terms and definitions
11 4 Symbols and abbreviated terms
4.1 Symbols
4.2 Abbreviated terms
13 5 Conventions
6 Wake-up and sleep features
6.1 Extension of physical coding sub-layer
15 6.2 Service primitives and interfaces
16 6.3 Power sequencing states
17 6.4 Command definitions
6.4.1 General
6.4.2 Low power sleep (LPS)
18 6.4.3 Wake-up request (WUR)
6.4.4 Wake-up pulse (WUP)
6.5 Generation of scrambling bits Sdn[2:0]
19 6.6 PCS PHY control state diagram
21 7 CTP test system and CTC structure
7.1 General
22 7.2 Test system set-up – Transmit test system
23 7.3 Test system set-up – Receive test system
24 7.4 CTC structure
25 8 PHY – Control IUT conformance test plan (with MII access)
8.1 PHY – Group 1: PHY control and timers (with MII access)
8.1.1 Overview
8.1.2 CTC_4.1.1 – PMA reset (with MII access)
26 8.1.3 CTC_4.1.2 – Value of minwait_timer – minwait_timer in TRAINING state (with MII access)
30 8.1.4 CTC_4.1.3 – Value of maxwait_timer (with MII access)
31 8.1.5 CTC_4.1.4 – Value of stabilize_timer (with MII access)
32 8.2 PHY – Group 2: PHY control state diagram (with MII access)
8.2.1 Overview
8.2.2 CTC_4.2.1 – PHY control state diagram – DISABLE TRANSMITTER state (with MII access)
33 8.2.3 CTC_4.2.2 – PHY control state diagram – SLAVE SILENT state (with MII access)
34 8.2.4 CTC_4.2.3 – PHY control state diagram – TRAINING state (with MII access)
37 8.2.5 CTC_4.2.4 – PHY control state diagram – SEND IDLE state (with MII access)
40 8.2.6 CTC_4.2.5 – PHY control state diagram – SEND IDLE OR DATA state (with MII access)
44 8.3 PHY – Group 3: PHY link monitor state diagram (with MII access)
8.3.1 Overview
45 8.3.2 CTC_4.3.1 – Link monitor state diagram – IUT does not enter the LINK OK state (with MII access)
47 9 PCS – IUT conformance test plan (with MII access)
9.1 PCS – Group 1: PCS transmit (with MII access)
9.1.1 Overview
48 9.1.2 CTC_3.1.1 – PCS signalling (with MII access)
50 9.1.3 CTC_3.1.2 – PCS reset (with MII access)
9.1.4 CTC_3.1.3 – PCS transmit proper SSD (with MII access)
51 9.1.5 CTC_3.1.4 – PCS transmit proper ESD (with MII access)
52 9.1.6 CTC_3.1.5 – PCS transmit ESD with tx_error (with MII access)
53 9.1.7 CTC_3.1.6 – PCS transmission of stuff bits (with MII access)
9.1.8 CTC_3.1.7 – PCS tx_error (with MII access)
55 9.2 PCS – Group 2: PCS transmit state diagram (with MII access)
9.2.1 Overview
9.2.2 CTC_3.2.1 – PCS transmit state diagram – SEND IDLE state (with MII access)
56 9.2.3 CTC_3.2.2 – PCS transmit state diagram – SSD1 VECTOR and SSD2 VECTOR states (with MII access)
9.2.4 CTC_3.2.3 – PCS transmit state diagram – SSD3 VECTOR state (with MII access)
58 9.2.5 CTC_3.2.4 – PCS transmit state diagram – TRANSMIT DATA state (with MII access)
59 9.2.6 CTC_3.2.5 – PCS transmit state diagram – ESD1 VECTOR state (with MII access)
9.2.7 CTC_3.2.6 – PCS transmit state diagram – ESD2 VECTOR state (with MII access)
60 9.2.8 CTC_3.2.7 – PCS transmit state diagram – ESD3 VECTOR state (with MII access)
61 9.2.9 CTC_3.2.8 – PCS transmit state diagram – ERR ESD1 VECTOR state (with MII access)
62 9.2.10 CTC_3.2.9 – PCS transmit state diagram – ERR ESD2 VECTOR state (with MII access)
63 9.2.11 CTC_3.2.10 – PCS transmit state diagram – ERR ESD3 VECTOR state (with MII access)
9.3 PCS – Group 3: PCS receive (with MII access)
9.3.1 Overview
9.3.2 CTC_3.3.1 – PCS receive signalling (with MII access)
64 9.3.3 CTC_3.3.2 – PCS automatic polarity detection (with MII access)
65 9.3.4 CTC_3.3.3 – PCS receive SSD (with MII access)
66 9.3.5 CTC_3.3.4 – PCS receive ESD (with MII access)
9.3.6 CTC_3.3.5 – PCS receive ERR ESD3 (with MII access)
67 9.3.7 CTC_3.3.6 – PCS reception of stuff bits (with MII access)
68 9.3.8 CTC_3.3.7 – PCS de-interleave ternary pairs (with MII access)
9.4 PCS – Group 4: PCS receive state diagram (with MII access)
9.4.1 Overview
9.4.2 CTC_3.4.1 – PCS receive state diagram (with MII access) – IDLE state
69 9.4.3 CTC_3.4.2 – PCS receive state diagram (with MII access) – CHECK SSD2 state
70 9.4.4 CTC_3.4.3 – PCS receive state diagram (with MII access) – CHECK SSD3 state
9.4.5 CTC_3.4.4 – PCS receive state diagram (with MII access) – SSD state
71 9.4.6 CTC_3.4.5 – PCS receive state diagram (with MII access) – BAD SSD state
72 9.4.7 CTC_3.4.6 – PCS receive state diagram (with MII access) – FIRST SSD state
73 9.4.8 CTC_3.4.7 – PCS receive state diagram (with MII access) – SECOND SSD state
74 9.4.9 CTC_3.4.8 – PCS receive state diagram (with MII access) – THIRD SSD state
9.4.10 CTC_3.4.9 – PCS receive state diagram (with MII access) – DATA state
75 9.4.11 CTC_3.4.10 – PCS receive state diagram (with MII access) – CHECK ESD2 state
76 9.4.12 CTC_3.4.11 – PCS receive state diagram (with MII access) – CHECK ESD3 state
77 9.4.13 CTC_3.4.12 – PCS receive state diagram (with MII access) – BAD ESD2 state
78 9.4.14 CTC_3.4.13 – PCS receive state diagram (with MII access) – BAD END and RX ERROR states
79 9.5 PCS – Group 5: PCS JAB state diagram (with MII access)
9.5.1 Overview
9.5.2 CTC_3.5.1 – PCS JAB state diagram (with MII access) – rcv_max_timer
80 10 PMA – IUT requirements and conformance test plan (with MII access)
10.1 PMA – Group 1: PMA electrical measurements (with MII access)
10.1.1 Overview
10.1.2 CTC_5.1.1 – PMA maximum transmitter output droop (with MII access)
81 10.1.3 CTC_5.1.2 – PMA transmitter distortion (with MII access)
82 10.1.4 CTC_5.1.3 – PMA transmitter timing jitter (with MII access)
83 10.1.5 CTC_5.1.4 – PMA transmitter power spectral density (PSD) (with MII access)
85 10.1.6 CTC_5.1.5 – PMA transmit clock frequency (with MII access)
86 10.1.7 CTC_5.1.6 – PMA MDI return loss (with MII access)
88 10.1.8 CTC_5.1.7 – PMA MDI mode conversion loss (with MII access)
91 10.1.9 CTC_5.1.8 – PMA transmitter peak differential output (with MII access)
92 10.2 PMA – Group 2: PMA receive tests (with MII access)
10.2.1 Group 2 overview
10.2.2 CTC_5.2.1 – PMA bit error rate verification (with MII access)
93 10.2.3 CTC_5.2.2 – PMA receiver frequency tolerance (with MII access)
94 10.2.4 CTC_5.2.3 – PMA alien crosstalk noise rejection (with MII access)
96 Annex A (informative) PHY control – Test suite
100 Annex B (normative) PCS – Test suite
119 Annex C (normative) PMA – Test system set-ups
132 Bibliography

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BS ISO 21111-6:2021
$215.11