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BSI 15/30317158 DC:2015 Edition

BSI 15/30317158 DC:2015 Edition

$45.21

BS ISO/IEC 14776-154. Information technology. Small Computer System Interface (SCSI). Part 154. Serial Attached SCSI — 3 (SAS-3)

Published By Publication Date Number of Pages
BSI 2015 340
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PDF Catalog

PDF Pages PDF Title
5 Contents
11 Tables
13 Figures
17 FOREWORD
18 INTRODUCTION
General
20 1 Scope
2 Normative references
22 3 Definitions, symbols, abbreviations, keywords, and conventions
3.1 Definitions
active cable assembly
alternating current (A.C.)
baud rate
bit error ratio (BER)
bit time
bounded uncorrelated jitter (BUJ)
burst time
byte
23 cable assembly
clock data recovery (CDR)
common SSC transmit clock
compliance point
compliant jitter tolerance pattern (CJTPAT)
connector
consecutive identical digits (CID)
cumulative distribution function (CDF)
D.C. idle
24 D.C. mode
data dependent jitter (DDJ)
decibel (dB)
dB millivolts (dBmV)
dB milliwatts (dBm)
decision feedback equalizer (DFE)
deterministic jitter (DJ)
direct current (D.C.)
disparity (see SPL-3)
dispersion
25 duty cycle distortion (DCD)
dword (see SPL-3)
electromagnetic interference (EMI)
enclosure
enclosure in port
enclosure out port
enclosure universal port
end device
end to end simulation
etch
26 expander device
expander phy
expander port
external connector
eye contour
fall time
fanout cable assembly
field
idle time
27 insertion loss
intersymbol interference (ISI)
jitter
jitter timing reference
jitter tolerance
jitter tolerance pattern (JTPAT)
least mean square (LMS)
managed connector category
28 near-end crosstalk (NEXT)
negation time
OOB burst
OOB idle
OOB interval
OOB sequence
OOB signal
optical mode
passive cable assembly
29 passive TxRx connection
phy
physical interconnect TxRx connection segment
PICS
physical link
physical link rate
power on
probe point
post cursor equalization ratio
Rpost
precursor equalization ratio
Rpre
30 random jitter
RJ
rate
receiver circuit
receiver circuit TxRx connection segment
RCCS
reference clock
receiver device
Rx
receiver device TxRx connection segment
RDCS
reference pulse response cursor
peak to peak
reference receiver device
reference sampling clock
31 reference sampling instant
reference transmitter device
reference transmitter test load
reflection coefficient
r
return loss
rise time
SAS device
SAS phy
SAS target device
32 SAS target device circuitry
SATA device
SATA phy
Serial ATA (SATA)
Serial Attached SCSI
SAS
signal
signal amplitude
signal level
signal time
signal tolerance
33 significant crosstalk
sinusoidal jitter
SJ
spread spectrum clocking
SSC
symbol
total jitter
TJ
trained
transceiver
transmitter circuit
transmitter circuit TxRx connection segment
TCCS
transmitter compliance transfer function
TCTF
34 transmitter device
Tx
transmitter device TxRx connection segment (TDCS)
TxRx connection
TxRx connection segment
unit interval (UI)
unmanaged active connector category
unmanaged passive connector category
untrained
usage variable
voltage modulation amplitude
VMA
35 waveform dispersion penalty
WDP
3.2 Symbols and abbreviations
3.2.1 Abbreviations
37 3.2.2 Units
38 3.2.3 Symbols
3.2.4 Mathematical operators
39 3.3 Keywords
invalid
mandatory
may
may not
obsolete
option, optional
prohibited
reserved
restricted
40 shall
should
vendor specific
3.4 Editorial conventions
41 3.5 Numeric and character conventions
3.5.1 Numeric conventions
3.5.2 Units of measure
42 3.5.3 Byte encoded character strings conventions
43 4 General
4.1 Physical links and phys
4.2 Phy test functions
44 5 Physical layer
5.1 Physical layer overview
5.2 Conventions for defining maximum limits for S-parameters
45 5.3 Compliance points
5.3.1 Compliance points overview
46 5.3.2 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s compliance points
54 5.3.3 12 Gbit/s compliance points
56 5.4 Interconnects
5.4.1 SATA connectors and cable assemblies
57 5.4.2 SAS connectors and cables
61 5.4.3 Connectors
5.4.3.1 Connectors overview
63 5.4.3.2 Connector categories
64 5.4.3.3 Recommended electrical performance limits for mated connector pairs supporting rates of 12 Gbit/s
65 5.4.3.4 SAS internal connectors
5.4.3.4.1 SAS Drive connectors
5.4.3.4.1.1 SAS Drive plug connector
66 5.4.3.4.1.2 SAS Drive cable receptacle connector
67 5.4.3.4.1.3 SAS Drive backplane receptacle connector
68 5.4.3.4.1.4 SAS Drive connector pin assignments
70 5.4.3.4.1.5 SAS MultiLink Drive plug connector
5.4.3.4.1.6 SAS MultiLink Drive cable receptacle connector
71 5.4.3.4.1.7 SAS MultiLink Drive backplane receptacle connector
5.4.3.4.1.8 SAS MultiLink Drive connector pin assignments
75 5.4.3.4.1.9 Micro SAS plug connector
5.4.3.4.1.10 Micro SAS receptacle connector
76 5.4.3.4.1.11 Micro SAS connector pin assignments
77 5.4.3.4.2 SAS 4i connectors
5.4.3.4.2.1 SAS 4i cable receptacle connector
5.4.3.4.2.2 SAS 4i plug connector
78 5.4.3.4.2.3 SAS 4i connector pin assignments
80 5.4.3.4.3 Mini SAS 4i connectors
5.4.3.4.3.1 Mini SAS 4i cable plug connector
5.4.3.4.3.2 Mini SAS 4i receptacle connector
81 5.4.3.4.3.3 Mini SAS 4i connector pin assignments
83 5.4.3.4.4 Mini SAS HD internal connectors
5.4.3.4.4.1 Mini SAS HD 4i cable plug connector
84 5.4.3.4.4.2 Mini SAS HD 8i cable plug connector
85 5.4.3.4.4.3 Mini SAS HD 4i receptacle connector
86 5.4.3.4.4.4 Mini SAS HD 8i receptacle connector
87 5.4.3.4.4.5 Mini SAS HD 16i receptacle connector
88 5.4.3.4.4.6 Mini SAS HD 4i connector pin assignments
91 5.4.3.5 SAS external connectors
5.4.3.5.1 Mini SAS 4x connectors
5.4.3.5.1.1 Mini SAS 4x cable plug connector
98 5.4.3.5.1.2 Mini SAS 4x receptacle connector
104 5.4.3.5.1.3 Mini SAS 4x connector pin assignments
105 5.4.3.5.1.4 Mini SAS 4x active connector pin assignments
106 5.4.3.5.1.5 Mini SAS 4x active cable power requirements
107 5.4.3.5.2 Mini SAS HD external connectors
5.4.3.5.2.1 Mini SAS HD 4x cable plug connector
108 5.4.3.5.2.2 Mini SAS HD 8x cable plug connector
109 5.4.3.5.2.3 Mini SAS HD 4x receptacle connector
110 5.4.3.5.2.4 Mini SAS HD 8x receptacle connector
111 5.4.3.5.2.5 Mini SAS HD 16x receptacle connector
112 5.4.3.5.2.6 Mini SAS HD 4x connector pin assignments
113 5.4.3.5.2.7 Mini SAS HD external connector management interface
114 5.4.3.5.2.8 Mini SAS HD external connector memory map
5.4.3.5.3 QSFP+ connectors
5.4.3.5.3.1 QSFP+ cable plug
115 5.4.3.5.3.2 QSFP+ receptacle
116 5.4.3.5.3.3 QSFP+ connector pin assignments
117 5.4.3.5.3.4 QSFP+ memory map
118 5.4.4 Cable assemblies
5.4.4.1 SAS internal cable assemblies
5.4.4.1.1 SAS Drive cable assemblies
120 5.4.4.1.2 SAS internal symmetric cable assemblies
5.4.4.1.2.1 SAS internal symmetric cable assemblies overview
121 5.4.4.1.2.2 SAS internal symmetric cable assembly – SAS 4i
122 5.4.4.1.2.3 SAS internal symmetric cable assembly – Mini SAS 4i
123 5.4.4.1.2.4 SAS internal symmetric cable assembly – Mini SAS HD 4i
124 5.4.4.1.2.5 SAS internal symmetric cable assembly – Mini SAS HD 8i
125 5.4.4.1.2.6 SAS internal symmetric cable assembly – SAS 4i to Mini SAS 4i with vendor-specific sidebands
126 5.4.4.1.2.7 SAS internal symmetric cable assembly – SAS 4i controller to Mini SAS 4i backplane with SGPIO
127 5.4.4.1.2.8 SAS internal symmetric cable assembly – Mini SAS 4i controller to SAS 4i backplane with SGPIO
128 5.4.4.1.2.9 SAS internal symmetric cable assembly – Mini SAS 4i to Mini SAS HD 4i
129 5.4.4.1.3 SAS internal fanout cable assemblies
5.4.4.1.3.1 SAS internal fanout cable assemblies overview
130 5.4.4.1.3.2 SAS internal controller-based fanout cable assemblies
133 5.4.4.1.3.3 SAS internal backplane-based fanout cable assemblies
136 5.4.4.2 SAS external cable assemblies
5.4.4.2.1 SAS external cable assemblies overview
137 5.4.4.2.2 SAS external cable assembly – Mini SAS 4x
140 5.4.4.2.3 SAS external cable assembly – Mini SAS HD 4x
142 5.4.4.2.4 SAS external cable assembly – Mini SAS HD 8x
144 5.4.4.2.5 SAS external cable assembly – Mini SAS HD 8x to Mini SAS HD 4x
146 5.4.4.2.6 SAS external cable assembly – Mini SAS HD 4x to Mini SAS 4x
147 5.4.4.2.7 SAS external cable assembly – QSFP+
5.4.5 Backplanes
148 5.5 TxRx connection characteristics
5.5.1 TxRx connection characteristics overview
149 5.5.2 TxRx connection general characteristics
150 5.5.3 Passive TxRx connection S-parameter limits
152 5.5.4 Passive TxRx connection characteristics for untrained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
153 5.5.5 Passive TxRx connection characteristics for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
154 5.5.6 Passive TxRx connection characteristics for trained 12 Gbit/s
157 5.5.7 TxRx connection characteristics for active cable assemblies
5.5.7.1 Active cable assembly electrical characteristics for trained 6 Gbit/s overview
158 5.5.7.2 Active cable assembly output electrical characteristics for trained 6 Gbit/s
159 5.5.7.3 Active cable assembly S-parameter limits for trained 6 Gbit/s and trained 12 Gbit/s
160 5.5.7.4 Active cable assembly electrical characteristics overview for 12 Gbit/s
161 5.5.7.5 Active cable assembly electrical characteristics for 12 Gbit/s
162 5.6 Test loads
5.6.1 Test loads overview
163 5.6.2 Zero-length test load
164 5.6.3 TCTF test load
169 5.6.4 Low-loss TCTF test load
170 5.6.5 Trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s reference transmitter test load
174 5.7 End to end simulation for trained 12 Gbit/s
5.7.1 End to end simulation for trained 12 Gbit/s overview
175 5.7.2 Usage models for end to end simulation for trained 12 Gbit/s
176 5.7.3 Reference transmitter equalization for trained 12 Gbit/s
178 5.7.4 Crosstalk measurement for end to end simulations and 12 Gbit/s jitter tolerance
179 5.8 Transmitter device and receiver device electrical characteristics
5.8.1 General electrical characteristics
180 5.8.2 Transmitter device and receiver device transients
181 5.8.3 Eye masks and the JTF
5.8.3.1 Eye masks overview
5.8.3.2 JTF
182 5.8.3.3 Transmitter device eye mask for untrained 1.5 Gbit/s and 3 Gbit/s
183 5.8.3.4 Receiver device eye mask for untrained 1.5 Gbit/s and 3 Gbit/s
5.8.3.5 Receiver device jitter tolerance eye mask for untrained 1.5 Gbit/s and 3 Gbit/s
185 5.8.4 Transmitter device characteristics
5.8.4.1 Transmitter device characteristics overview
5.8.4.2 Transmitter device coupling requirements
5.8.4.3 Transmitter device general electrical characteristics
187 5.8.4.4 Transmitter device signal output characteristics for untrained 1.5 Gbit/s and 3 Gbit/s as measured with the zero-length test load
188 5.8.4.5 Transmitter device signal output characteristics for untrained 1.5 Gbit/s and 3 Gbit/s as measured with each test load
190 5.8.4.6 Transmitter device signal output characteristics for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
5.8.4.6.1 Transmitter device signal output characteristics for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s overview
191 5.8.4.6.2 Trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s transmitter device test procedure
192 5.8.4.6.3 Trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s Transmitter device S-parameter limits
193 5.8.4.6.4 Recommended trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s transmitter device settings for interoperability
194 5.8.4.6.5 Trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s reference transmitter device characteristics
195 5.8.4.6.6 Trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s Transmitter equalization, VMA, and VP-P measurement
197 5.8.4.7 Transmitter device signal output characteristics for trained 12 Gbit/s
5.8.4.7.1 Transmitter device signal output characteristics for trained 12 Gbit/s overview
204 5.8.4.7.2 12 Gbit/s Transmitter device S-parameter limits
206 5.8.4.7.3 12 Gbit/s reference transmitter device
208 5.8.4.7.4 Transmitter device end to end simulation characteristics for trained 12 Gbit/s
209 5.8.4.7.5 Transmitter device signal output characteristics at CTS for 12 Gbit/s when an active cable is connected
5.8.4.8 Transmitter device signal output characteristics for OOB signals
211 5.8.5 Receiver device characteristics
5.8.5.1 Receiver device characteristics overview
5.8.5.2 Receiver device coupling requirements
212 5.8.5.3 Receiver device general electrical characteristics
214 5.8.5.4 Delivered signal characteristics for untrained 1.5 Gbit/s and 3 Gbit/s
215 5.8.5.5 Maximum delivered jitter for untrained 1.5 Gbit/s and 3 Gbit/s
216 5.8.5.6 Receiver device jitter tolerance for untrained 1.5 Gbit/s and 3 Gbit/s
217 5.8.5.7 Receiver device and delivered signal characteristics for trained 1.5 Gbit/s, 3 Gbit/s, 6 Gbit/s, and 12 Gbit/s
5.8.5.7.1 Delivered signal characteristics for trained 1.5 Gbit/s, 3 Gbit/s, 6 Gbit/s, and 12 Gbit/s
5.8.5.7.2 Receiver device S-parameter limits
218 5.8.5.7.3 Reference receiver device characteristics
5.8.5.7.3.1 Reference receiver device overview
220 5.8.5.7.3.2 Reference receiver device DFE
5.8.5.7.3.3 Reference receiver device equalization for trained 12 Gbit/s
221 5.8.5.7.4 Reference receiver device termination characteristics for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
5.8.5.7.5 Reference receiver device termination characteristics for trained 12 Gbit/s
222 5.8.5.7.6 Stressed receiver device jitter tolerance test
5.8.5.7.6.1 Stressed receiver device jitter tolerance test overview for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
224 5.8.5.7.6.2 Stressed receiver device jitter tolerance test procedure for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
225 5.8.5.7.6.3 Test equipment calibration and ISI generator calibration for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
5.8.5.7.6.4 Crosstalk source calibration for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
226 5.8.5.7.6.5 Stressed receiver device jitter tolerance test procedure for trained 12 Gbit/s
5.8.5.7.6.6 ISI generator calibration for trained 12 Gbit/s
229 5.8.5.7.6.7 Crosstalk calibration for trained 12 Gbit/s stressed receiver device jitter tolerance test
5.8.5.7.6.8 Applied RJ for trained 12 Gbit/s stressed receiver device jitter tolerance test
5.8.5.7.6.9 Applied SJ
231 5.8.5.8 Delivered signal characteristics for OOB signals
5.8.6 Spread spectrum clocking (SSC)
5.8.6.1 SSC overview
232 5.8.6.2 Transmitter SSC modulation
233 5.8.6.3 Receiver SSC modulation tolerance
234 5.8.6.4 Expander device center-spreading tolerance buffer
235 5.8.7 Non-tracking clock architecture
5.9 READY LED signal electrical characteristics
236 5.10 POWER DISABLE signal electrical characteristics
238 5.11 Out of band (OOB) signals
5.11.1 OOB signals overview
239 5.11.2 Transmitting OOB signals
241 5.11.3 Receiving OOB signals
242 5.11.4 Transmitting the SATA port selection signal
243 Annex A
Jitter tolerance pattern (JTPAT)
245 Annex B
SASWDP
B.1 SASWDP introduction
B.2 SASWDP.m
252 B.3 SASWDP_testcase.m
254 Annex C
StatEye
C.1 StatEye introduction
C.2 analysis.py
255 C.3 cdr.py
256 C.4 extractJitter.py
258 C.5 penrose.py
260 C.6 portalocker.py
263 C.7 stateye.py
278 C.8 touchstone.py
286 C.9 testcase.py
291 C.10 testall.py
294 C.11 File StatEye_readme.pdf
C.11.1 How to install and run the SAS-2.1 StatEye
295 Annex D
End to end simulation for trained 12 Gbit/s
D.1 Detailed end to end simulation procedure description for trained 12 Gbit/s
297 D.2 Trained 12 Gbit/s usage models, S-parameter files, and crosstalk amplitude
D.2.1 Transmitter device connected to a separable passive TxRx connection segment
299 D.2.2 Transmitter device connected to a non-separable passive TxRx connection segment
302 D.2.3 TxRx connection segment
303 D.2.4 Stressed Receiver device delivered signal calibration end to end simulation diagram
305 Annex E
12 Gbit/s S-parameters and end to end simulation
E.1 S-parameters for 12 Gbit/s simulation
E.1.1 Measurement procedure
306 E.1.2 Multiple channel segments
307 E.2 End to end simulation using SAS3_EYEOPENING
308 Annex F
Signal performance measurements
F.1 Signal performance measurements overview
F.2 Glossary
port:
F.3 Simple physical link
F.3.1 Simple physical link overview
309 F.3.2 Assumptions for the structure of the transmitter device and the receiver device
310 F.3.3 Definition of receiver sensitivity and receiver device sensitivity
311 F.4 Signal measurement architecture
F.4.1 General
F.4.2 Relationship between signal compliance measurements at interoperability points and operation in systems
312 F.5 De-embedding connectors in test fixtures
F.6 De-embedding test fixture for 12 Gbit/s transmitter compliance
313 F.7 Measurement conditions for signal output at the transmitter device
314 F.8 Measurement conditions for signal tolerance at the transmitter device
316 F.9 Measurement conditions for signal output at the receiver device
F.10 Measurement conditions for signal tolerance at the receiver device
317 F.11 S-parameter measurements
F.11.1 S-parameter overview
F.11.2 S-parameter naming conventions
318 F.11.3 Use of single ended instrumentation in differential applications
320 F.11.4 Measurement configurations for physical link elements
F.11.4.1 Measurement configuration overview
F.11.4.2 Transmitter device S22 measurements
321 F.11.4.3 Receiver device S11 measurements
F.11.4.4 TxRx connection S11 measurements at IT or CT
322 F.11.4.5 TxRx connection S22 measurements at IR or CR
323 F.12 Calibration of JMDs
F.12.1 Calibration of JMDs overview
F.12.1.1 Purpose of JMD calibration
F.12.1.2 Overview of low frequency calibration for SSC configurations
325 F.12.1.3 Overview of low frequency calibration for non-SSC configurations
F.12.1.4 High frequency calibration
326 F.12.2 JMD calibration procedure
F.12.2.1 General characteristics and equipment
327 F.12.2.2 Calibration of the JMD for testing SSC configurations
328 F.12.2.3 Calibration of the JMD for testing non-SSC configurations
330 Annex G
Description of the included Touchstone models for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
G.1 Description of included Touchstone models for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s overview
G.2 Reference transmitter device termination model for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
331 G.3 Reference receiver device termination model for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
332 G.4 Generic return loss circuit model for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
333 G.5 Reference transmitter test load for trained 1.5 Gbit/s, 3 Gbit/s, and 6 Gbit/s
336 Annex H
Mini SAS 4x active cable assembly power supply and voltage detection circuitry
337 Annex I
SAS icons
339 Annex J
Standards bodies contact information
340 Bibliography

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BSI 15/30317158 DC
$45.21