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BSI PD IEC/TR 63072-1:2017

$198.66

Photonic integrated circuits – Introduction and roadmap for standardization

Published By Publication Date Number of Pages
BSI 2017 54
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This part of IEC 63072, which is a Technical Report, provides an introduction to photonic integrated circuits (PICs) and describes a roadmap for the standardization of PIC technology over the next decade.

NOTE The trademarks and trade names mentioned in this document are given for the convenience of users of this document; this does not constitute an endorsement by IEC of these companies.

PDF Catalog

PDF Pages PDF Title
2 National foreword
6 CONTENTS
9 FOREWORD
11 1 Scope
2 Normative references
3 Terms and definitions
13 4 Photonic integrated circuit (PIC)
4.1 Overview
15 4.2 PIC families
4.2.1 General
Figures
Figure 1 – Examples of PICs [1]
16 4.2.2 Silicon photonics
4.2.3 III-V photonics
4.2.4 Silica and silicon nitride PICs
Figure 2 – Optical beam forming network fabricated in TriPleX (silicon nitride)
17 4.3 Manufacturing capabilities
4.4 Global market
4.5 Global government investment in PIC research and development
4.5.1 General
4.5.2 United States of America
4.5.3 Europe
4.5.4 Japan
18 5 Silicon photonics
5.1 Overview
5.2 Integration schemes
5.2.1 General
Figure 3 – Typical silicon waveguides [6]
19 5.2.2 Heterogeneous integration
5.2.3 Homogenous integration
5.3 Non-linear behaviour
6 III-V photonics
6.1 Indium phosphide (InP) photonics
Figure 4 – Heterogeneous integration by flip chip and copper pillars
20 Figure 5 – Indium phosphide PIC with many structures, including AWG
21 7 PIC transceiver – A simple example
7.1 Overview
7.2 Transmitter section
Figure 6 – Combined InP and TriPleX microwave photonic beam-forming network
22 7.3 Receiver section
Figure 7 – Schematic of four channel PIC transceiver by Luxtera [6]
23 8 Optical sources
8.1 Overview
8.2 Advances in III-V integration onto silicon PICs
24 8.3 Vertical cavity surface emitting lasers (VCSELs)
9 Optical receivers
Figure 8 – Schematic view of 3D assembly of PIC + EIC electro-optical assembly [6]
25 10 Modulators
10.1 Overview
10.2 Common modulator structures
Figure 9 – Example of Ge-on-Si photodetector formed by germanium selective epitaxy [6]
26 10.3 Plasma dispersion effect
Figure 10 – High speed PN modulator [6]
27 10.4 Plasmonics
10.5 Silicon organic hybrid
Figure 11 – PETRA optical I/O core chip modulation scheme
28 11 Switches
11.1 Overview
11.2 Mach-Zehnder interferometers (MZI)
11.3 Micro-ring resonator (MRR)
Figure 12 – Silicon organic hybrid
29 11.4 Double-ring assisted MZI (DR-MZI)
12 3D integration
12.1 Optochip
12.2 Through-silicon-vias (TSVs)
Figure 13 – 4 x 4 switching matrix PIC attached to PCB with wire bonds on the EU FP7 PhoxTroT project
30 12.3 Hybrid integration process example
12.4 Flip-chip bonding
Figure 14 – EU FP7 project PhoxTroT 3D integrated optochip concept
31 12.5 State of the art in 3D research and development
13 Commercial state of the art
13.1 Overview
13.2 Luxtera
Figure 15 – LIFT principle
32 13.3 Intel
13.4 Mellanox
33 13.5 Oracle
13.6 IBM
13.7 Photonics Electronics Technology Research Association (PETRA)
Figure 16 – PETRA optical I/O core performance at 25 Gb/s
34 14 PIC coupling interfaces
14.1 Overview
14.2 Grating coupler
35 Figure 17 – Examples of vertical grating couplers [6]
36 Figure 18 – Coupling efficiency of single polarization grating coupler (SPGC) at 1 310 nm and 1 490 nm [91]
Figure 19 – Composite coupling interfaces on PETRA optical I/O core
37 14.3 Adiabatic coupling
Figure 20 – Assembly for adiabatic optical coupling between Si photonics chip and SM polymer waveguide
38 Figure 21 – Flip-chipped silicon photonic chip onto polymer waveguide substrate using adiabatic coupling
39 14.4 Butt coupling
14.5 Orthogonal chip-to-fibre coupling
Figure 22 – Bidirectional optical coupling between SOI waveguides and single polymer waveguides
40 15 Electrical interface
Figure 23 – Design of the mirror plug assembly
41 16 Packaging
17 Standardization roadmap
Figure 24 – Typical operative framework of silicon-photonics modules
42 Figure 25 – PIC standardization roadmap
43 Bibliography
BSI PD IEC/TR 63072-1:2017
$198.66