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BSI PD IEC/TS 62686-1:2012

$198.66

Process management for avionics. Electronic components for aerospace, defence and high performance (ADHP) applications – General requirements for high reliability integrated circuits and discrete semiconductors

Published By Publication Date Number of Pages
BSI 2012 66
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This part of IEC 62686 defines the minimum requirements for general purpose “off the shelf” COTS (commercial off-the-shelf) integrated circuits and discrete semiconductors for ADHP (Aerospace, Defence and High Performance) applications.

This Technical Specification applies to all components that can be operated in ADHP applications within the manufacturers’ publicly available datasheet limits in conjunction with IEC/TS 62239-1. It may be used by other high performance and high reliability industries, at their discretion.

ADHP application requirements may not necessarily be fulfilled by this specification alone. ADHP OEMs (original equipment manufacturers) may need to consider redesigning their products or conducting further testing to verify suitability in ADHP applications using their IEC/TS 62239-1 ECMP procedures. Alternatively a component in accordance with IEC/TS 62564-1 may be more suitable.

PDF Catalog

PDF Pages PDF Title
4 CONTENTS
7 FOREWORD
9 INTRODUCTION
10 1 Scope
2 Normative references
14 3 Terms, definitions and abbreviations
3.1 Terms and definitions
16 3.2 Abbreviations
18 4 Technical requirements
4.1 General
4.2 Procedures
4.2.1 General
4.2.2 Product discontinuance
4.2.3 ESD protection during manufacture
19 4.2.4 Specification control
4.2.5 Traceability
4.3 Product or process change notification (PCN)
4.3.1 General
4.3.2 Notification
4.3.3 Notification details
20 4.3.4 Notifiable changes
4.4 Shipment controls
4.4.1 General
4.4.2 Shipping container and date code marking
4.4.3 Date code remarking
4.4.4 Inner container formation
21 4.4.5 Date code age on delivery
4.4.6 ESD marking
4.4.7 MSL
4.4.8 Lead-free marking
4.4.9 Labels
22 4.5 Electrical
4.5.1 General
4.5.2 Electrical test
4.5.3 Electrical parameter assessment
4.5.4 SDRAM memories
Tables
Table 1 – Label requirements
23 4.5.5 Logic families
4.5.6 Power MOSFETs
4.5.7 Silicon rectifier diodes
4.6 Mechanical
4.6.1 General
4.6.2 Device or shipping container marking
4.6.3 Small packages
4.6.4 Moisture sensitivity
4.6.5 Robustness of hermetic seals
24 4.6.6 Termination finishes
4.7 Audit capability
4.7.1 General
4.7.2 Internal quality audits
4.7.3 Subcontract manufacturing
Table 2 – Internal quality audit requirements
25 4.8 Quality assurance
4.8.1 General
4.8.2 Quality system
4.8.3 Sampling plans
4.8.4 Failure analysis support
4.8.5 Outgoing quality
26 4.9 Supplier performance monitoring by the user
4.9.1 General
4.9.2 Lot acceptance
Table 3 – Outgoing quality
Table 4 – Incoming test
27 4.9.3 Suspension of deliveries
4.9.4 Loss of approval
4.9.5 AQL figures
4.9.6 100 % screening
4.9.7 Termination determination
4.10 Qualification
4.10.1 General
28 4.10.2 Methodology
29 4.10.3 Test samples
30 4.10.4 Qualification categories
4.10.5 Maintenance of qualification standard
4.10.6 In-process test results
31 Table 5 – Technology/family qualification and device qualification
34 4.10.7 Product monitor results
4.10.8 References
4.10.9 Qualification report
4.10.10 Archiving
4.10.11 Qualification by similarity
4.10.12 Similarity assessment
35 4.11 Reliability
4.11.1 General
4.11.2 Operating reliability
4.11.3 Failure criteria
36 4.11.4 Corrective action
4.11.5 Warranty
4.11.6 Suspension of certification
4.11.7 Single event effects (SEE)
4.12 Product monitor
4.12.1 General
4.12.2 Monitor programme
Table 6 – Operating life failure rates
37 4.12.3 Problem notification
4.12.4 Data reporting
4.12.5 Samples
4.12.6 Production maturity factors
4.12.7 Device dissipation
Table 7 – Production maturity factors
38 4.12.8 Corrective action
4.12.9 Product monitor results
4.12.10 Accumulated test data
4.13 Environmental, health and safety (EHS)
4.13.1 General
Table 8 – Product monitor tests
39 4.13.2 EHS compliance
4.13.3 Device handling
4.13.4 Device materials
4.14 Shipping container
4.14.1 General
4.14.2 ESD requirements
40 4.14.3 Magazine reuse
4.14.4 Tubes
41 4.14.5 Trays
4.15 Compliance with internal standards
42 Annex A (informative) Test code (TC) information
44 Table A.1 – Conditions of the DC over voltage stress methodof JP001.01 or IEC 62416 test
46 Table A.2 – Examples of temperature acceleration factors
47 Table A.3 – Test conditions
49 Table A.4 – Relationship between write/erase cycle and data retention
56 Annex B (informative) Cross-reference to STACK specification S/0001 revision 14
63 Bibliography
BSI PD IEC/TS 62686-1:2012
$198.66