BSI PD IEC TS 63107:2020
$167.15
Integration of internal arc-fault mitigation systems in power switchgear and controlgear assemblies (PSC assemblies) according to IEC 61439-2
| Published By | Publication Date | Number of Pages |
| BSI | 2020 | 42 |
This document states requirements for integration and testing of IAMS in low-voltage switchgear and controlgear assemblies – power switchgear and controlgear assemblies according to IEC 61439-1 and IEC 61439-2 (PSC-assemblies) to demonstrate their correct operation.
This document does not address personnel safety or damage to the PSC-assembly. These requirements are dealt with in IEC TR 61641 (see also 10.10.1).
NOTE This document can be used as a reference for other types of assemblies in the IEC 61439 series, but adaptation of the test procedures and acceptance criteria can apply taking into account the specifics of such other assemblies or products.
IAMS consist of IACDs and IARDs complying with their relevant product standard (e.g. optical based IACDs in accordance with IEC 60947-9-2, AQDs in accordance with IEC 60947-9-1 and SCPD’s in accordance with IEC 60947-2). For the reliable function in a PSC-assembly, the verification of correct operation of the complete system under built-in conditions is addressed.
This document applies only to enclosed PSC-assemblies and deals with all required verifications needed for the integration in conjunction with IEC 61439-1 and IEC 61439-2.
The test procedure given in this document takes into consideration:
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the correct function of the IAMS within the PSC-assembly;
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the prevention of unintended operation of the IAMS within the PSC-assembly;
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the functioning behaviour of the system immediately after the assembly is energised.
Different tests under more severe conditions (e.g. doors in open position) can be performed with an agreement between the user and the original manufacturer of the PSC-assembly.
This document does not supersede any individual product standard. Individual devices are required to comply with their relevant standard.
This document does not apply to integration of arc fault detection devices (AFDD) according to IEC 62606.
The informative Annex II gives guidance on particular constructional requirements for incorporation of IAMS within a PSC-assembly.
The informative Annex HH gives guidance for the user of PSC-assemblies about the criteria to be considered when specifying a PSC-assembly with an integrated IAMS.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 2 | undefined |
| 4 | English CONTENTS |
| 5 | FOREWORD |
| 7 | INTRODUCTION |
| 9 | 1 Scope 2 Normative references |
| 10 | 3 Terms and definitions |
| 12 | 4 Symbols and abbreviated terms 5 Interface characteristics 6 Information Table 1 – Symbols and abbreviated terms |
| 13 | 7 Service conditions 8 Constructional requirements |
| 14 | 9 Performance requirements |
| 15 | 10 Design verification |
| 24 | 11 Routine verification |
| 26 | Annex HH(informative)Guidance for the user of PSC-assemblies about the aspects to be considered when specifying a PSC-assembly with an integrated IAMS HH.1 General information |
| 27 | HH.2 Influence of the electrical parameters of the supply Figure HH.1 – Time/current characteristic curves NH- Fuse-links Size 000 – 3 gG AC 400 V IEC 60269-2 |
| 28 | HH.3 Interaction with other devices/systems in the PSC-assembly Figures |
| 30 | Annex II(informative)Guidance for the original manufacturer of PSC-assemblies on construction requiring particular attention when incorporating IAMS II.1 Selection of devices forming parts of an IAMS II.2 Installation of switching devices and components |
| 31 | II.3 Accessibility |
| 32 | Annex JJ(informative)Description of the extinction of an internal arc-fault in a PSC-assembly by an IAMS using an AQD during testing JJ.1 General JJ.2 Circuit diagram and event description Figure JJ.1 – Circuit diagram |
| 33 | JJ.3 Selected oscillograms Figure JJ.2 – Incoming currents at the beginning of the sequence |
| 34 | Figure JJ.3 – Currents and voltages at the incoming terminals at the end of the sequence |
| 35 | Figure JJ.4 – Currents in the AQD circuit |
| 36 | Figure JJ.5 – Currents in the arc-fault circuit |
| 37 | Figure JJ.6 – Currents in the arc-fault circuit, curves magnified |
| 38 | Figure JJ.7 – Voltages at the incoming terminals |
| 39 | Figure JJ.8 – Electrical energy caused by the arc-fault currents and the voltages at the incoming terminals with t0 as the start point for calculation |
| 40 | Bibliography |
