IEC 62142:2005
$74.75
Verilog (R) register transfer level synthesis
| Published By | Publication Date | Number of Pages |
| IEC | 2005-06-27 | 116 |
Defines a set of modeling rules for writing Verilog®
HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL
are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.
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