IEC 62530:2011

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SystemVerilog – Unified Hardware Design, Specification, and Verification Language

Published By	Publication Date	Number of Pages
IEC	2011-05-19	1111

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Categories: 25.040.01 - Industrial automation systems in general, IEC

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Description

IEC 62530:2011(E) Provides a unified Hardware Design, Specification, and Verification language. IEEE Std 1364TM-2005 Verilog is a design language. Both standards were approved by the IEEE-SASB in November 2005. This standard creates new revisions of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog standards, which include errata fixes and resolutions, enhancements, enhanced assertion language, merger of Verilog Language Reference Manual (LRM) and SystemVerilog 1800 LRM into a single LRM, integration with Verilog-AMS, and ensures interoperability with other languages such as SystemC and VHDL. This publication has the status of a double logo IEEE/IEC standard.

Additional information

Published Code	IEC
Published By	International Electrotechnical Commission
Publication Date	2011-05-19
Pages Count	1111
Language	English
Edition	2.0
File Size	4.6 MB
ICS Codes	25.040.01 - Industrial automation systems in general

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IEC 62530:2011

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