IEEE 1005 1999
$72.04
IEEE Standard for Definitions, Symbols, and Characterization of Floating Gate Memory Arrays
| Published By | Publication Date | Number of Pages |
| IEEE | 1999 | 129 |
Revision Standard – Inactive – Withdrawn. This standard describes the underlying physics and the operation of floating gate memory arrays, specifically, UV erasable EPROM, byte rewritable E 2 PROMs, and block rewritableflash EEPROMs. In addition, reliability hazards are covered with focus on retention, endurance,and disturb. There are also clauses on the issues of testing floating gate arrays and their hardness to ionizing radiation.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 1 | Title Page |
| 3 | Introduction Participants |
| 5 | CONTENTS |
| 7 | 1. Overview 1.1 Scope 1.2 Document organization |
| 8 | 1.3 Basic physics of floating gate nonvolatile devices |
| 23 | 1.4 Introduction to floating gate memory arrays |
| 24 | 2. References |
| 25 | 3. Definitions, abbreviations and acronyms, and symbols 3.1 Definitions |
| 32 | 3.2 Acronyms and abbreviations |
| 33 | 3.3 Symbols 4. Basic floating gate FET types 4.1 Background |
| 34 | 4.2 EPROM |
| 46 | 4.3 E2PROM |
| 50 | 4.4 Flash memory cells |
| 81 | 5. Reliability considerations 5.1 Background 5.2 Failure rate components unique to floating gate devices |
| 82 | 5.3 MOS failure mechanisms 5.4 Effect of retention on failure rate |
| 84 | 5.5 Effect of endurance on failure rate |
| 85 | 5.6 Determination of composite failure rate 5.7 Calculation of the composite failure rate |
| 87 | 5.8 Conclusion 6. Retention 6.1 Background |
| 88 | 6.2 Concept of retention |
| 90 | 6.3 Verification of retention |
| 91 | 6.4 Discharge of capacitor by F-N tunneling |
| 92 | 7. Endurance 7.1 Background 7.2 Endurance concept |
| 95 | 7.3 Endurance rating objectives |
| 96 | 7.4 Endurance verification approaches |
| 98 | 8. Disturbs 8.1 Introduction 8.2 Basic disturb mechanisms |
| 102 | 8.3 Program and erase disturbs |
| 105 | 8.4 Effects enhancing disturbs |
| 106 | 9. Testing methodology 9.1 Background 9.2 Failure definition |
| 107 | 9.3 Methods of tests 9.4 Write conditions |
| 109 | 9.5 Power-supply sequence of EEPROMs 9.6 Test patterns |
| 110 | 9.7 Retention test conditions |
| 111 | 9.8 Endurance test conditions |
| 112 | 9.9 Appendix |
| 114 | 10. Ionizing radiation effects on floating gate memory ICs 10.1 Radiation effects background |
| 116 | 10.2 Measurement of radiation effects |
| 117 | 10.3 Total dose tests |
| 118 | 10.4 Dose-rate tests |
| 120 | 10.5 SEP tests |
| 121 | 11. Other nonvolatile semiconductor structures 11.1 Background 11.2 Other semiconductor nonvolatile technologies |
| 122 | 11.3 Non-memory applications of nonvolatile floating gate technology |
| 123 | 12. Bibliography |
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