IEEE 1012-2016(Redline)

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IEEE Standard for System, Software, and Hardware Verification and Validation (Redline)

Published By	Publication Date	Number of Pages
IEEE	2016

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Category: IEEE

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Description

Revision Standard – Active. Verification and validation (V&V) processes are used to determine whether the development products of a given activity conform to the requirements of that activity and whether the product satisfies its intended use and user needs. V&V life cycle process requirements are specified for different integrity levels. The scope of V&V processes encompasses systems, software, and hardware, and it includes their interfaces. This standard applies to systems, software, and hardware being developed, maintained, or reused (legacy, commercial off-the-shelf [COTS], non-developmental items). The term software also includes firmware and microcode, and each of the terms system, software, and hardware includes documentation. V&V processes include the analysis, evaluation, review, inspection, assessment, and testing of products.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1012™-2016 Front Cover
2	Title page
4	Important Notices and Disclaimers Concerning IEEE Standards Documents
7	Participants IEEE Std 1012-2016
9	Participants IEEE Std 1012-2016/Cor1-2017
11	Introduction
13	Contents
16	1. Overview 1.1 Scope
17	1.2 Purpose
18	1.3 Field of application
19	1.4 V&V objectives 1.5 Organization of the standard
22	1.6 Audience 1.7 Conformance 1.8 Disclaimer
23	2. Normative references 3. Definitions and acronyms 3.1 Definitions
27	3.2 Acronyms
28	4. Relationships between verification and validation (V&V) and life cycle processes
33	5. Integrity levels
35	6. V&V process overview 6.1 General
36	6.2 V&V testing
38	7. Common V&V processes 7.1 V&V management process
39	7.2 Acquisition Support V&V process
40	7.3 Supply Planning V&V process 7.4 Project Planning V&V process
41	7.5 Configuration Management V&V process
51	8. System V&V processes 8.1 Business or Mission Analysis V&V process 8.2 Stakeholder Needs and Requirements Definition V&V process
52	8.3 System Requirements Definition V&V process
53	8.4 Architecture definition V&V process
54	8.5 Design Definition V&V process
55	8.6 System analysis V&V process
56	8.7 Implementation V&V process
57	8.8 Integration V&V process
58	8.9 Verification process
59	8.10 Transition V&V process
60	8.11 Validation process 8.12 Operation V&V process
61	8.13 Maintenance V&V process
62	8.14 Disposal V&V process
95	9. Software V&V processes 9.1 Software Concept V&V process 9.2 Software Requirements Analysis V&V process
96	9.3 Software Design V&V process
97	9.4 Software Construction V&V process
99	9.5 Software Integration V&V process 9.6 Software Qualification Testing V&V process
100	9.7 Software Acceptance Testing V&V process
101	9.8 Software Verification process 9.9 Software Installation and Checkout V&V process
102	9.10 Software Validation process
103	9.11 Software Operation V&V process 9.12 Software Maintenance V&V process
105	9.13 Software Disposal V&V process
140	10. Hardware V&V processes 10.1 Hardware Concept V&V process
141	10.2 Hardware Requirements Analysis V&V process 10.3 Hardware Design V&V process
142	10.4 Hardware Fabrication V&V process
144	10.5 Hardware Integration V&V process 10.6 Hardware Qualification Testing V&V process
145	10.7 Hardware Acceptance Testing V&V process
146	10.8 Hardware Verification process 10.9 Hardware Transition V&V process
147	10.10 Hardware Validation process
148	10.11 Hardware Operation V&V process 10.12 Hardware Maintenance V&V process
149	10.13 Hardware Disposal V&V process
178	11. V&V reporting, administrative, and documentation requirements 11.1 V&V reporting requirements
182	11.2 V&V administrative requirements 11.3 V&V documentation requirements
183	12. V&V plan 12.1 Overview
184	12.2 VVP Section 1: Purpose 12.3 VVP Section 2: Referenced documents 12.4 VVP Section 3: Definitions 12.5 VVP Section 4: V&V overview
185	12.6 VVP Section 5: V&V processes
186	12.7 VVP Section 6: V&V reporting requirements 12.8 VVP Section 7: V&V administrative requirements
187	12.9 VVP Section 8: V&V test documentation requirements
188	Annex A (informative) Mapping of IEEE 1012 verification and validation (V&V) activities and tasks A.1 Mapping of ISO/IEC/IEEE 15288 activities to IEEE 1012 V&V activities and tasks
191	A.2 Mapping of IEEE 1012 V&V activities to ISO/IEC/IEEE 15288 system life cycle processes and activities
193	A.3 Mapping of ISO/IEC 12207 V&V activities to IEEE 1012 V&V activities and tasks
195	A.4 Mapping of IEEE 1012 V&V activities to ISO/IEC 12207 software life cycle processes and activities
197	Annex B (informative) A risk-based integrity level schema
199	Annex C (informative) Definition of independent verification and validation (IV&V) C.1 Independence parameters C.1.1 Introduction C.1.2 Technical independence C.1.3 Managerial independence C.1.4 Financial independence C.2 Forms of independence C.2.1 Introduction
200	C.2.2 Classical IV&V C.2.3 Modified IV&V C.2.4 Integrated IV&V
201	C.2.5 Internal IV&V C.2.6 Embedded V&V
202	Annex D (informative) V&V of reuse software D.1 Purpose D.2 V&V of software developed in a reuse process D.2.1 Introduction
203	D.2.2 V&V of assets in development D.2.3 V&V of reused assets D.3 V&V of software developed and reused outside of a reuse process
208	Annex E (informative) Verification and validation (V&V) measures E.1 Introduction E.2 Measures for evaluating anomaly density
209	E.3 Measures for evaluating V&V effectiveness E.4 Measures for evaluating V&V efficiency
211	Annex F (informative) Example of verification and validation (V&V) relationships to other project responsibilities
212	Annex G (informative) Optional verification and validation (V&V) tasks
218	Annex H (informative) Environmental factors consideration H.1 Introduction H.2 In the agreement processes
219	H.3 In the organizational project-enabling processes H.4 In the project processes H.5 In the technical processes
221	Annex I (informative) Verification and validation (V&V) of system, software, and hardware integration I.1 Introduction
222	I.2 Examples of system failures caused by integration issues I.2.1 Introduction I.2.2 Year 2000 system integration issue I.2.3 System architecture integration issues
223	I.2.4 System, software, and hardware interaction issues
226	Annex J (informative) Hazard, security, and risk analysis J.1 Introduction
227	J.2 Hazard analysis
228	J.3 Security analysis J.3.1 Summary
229	J.3.2 Threat-based security analysis J.3.2.1 Overview
230	J.3.2.2 Typical threats
233	J.3.2.3 Typical vulnerabilities
235	J.3.3 Process assurance consideration in system life cycle
236	J.4 Risk analysis J.4.1 Risk analysis objectives J.4.2 Risk analysis context
237	J.4.3 V&V risk analysis J.4.3.1 Risk identification
238	J.4.3.2 Risk estimation J.4.3.3 Risk evaluation
239	Annex K (informative) Example of assigning and changing the system integrity level of “supporting system functions”
241	Annex L (informative) Mapping of ISO/IEC/IEEE 15288 and ISO/IEC 12207 process outcomes to verification and validation (V&V) tasks
256	Annex M (informative) Verification and validation (V&V) of nth of a kind systems
258	Annex N (informative) Bibliography
260	Back Cover