IEEE 1076.1-1999

$112.67

IEEE Standard VHDL Analog and Mixed-Signal Extensions

Published By	Publication Date	Number of Pages
IEEE	1999	298

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Description

New IEEE Standard – Superseded. This standard defines the IEEE 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDL-AMS, is built on IEEE Std 1076-1993 (VHDL) and extends it with additions and changes to provide capabilities of writing and simulating analog and mixed-signal models.

PDF Catalog

PDF Pages	PDF Title
1	Title Page
3	Introduction
4	Participants
8	CONTENTS
11	0. Overview 0.1 Purpose and scope 0.2 Standards used as references
12	0.3 Structure and terminology of this document
15	1. Design entities and configurations 1.1 Entity declarations
20	1.2 Architecture bodies
22	1.3 Configuration declarations
28	2. Subprograms and packages 2.1 Subprogram declarations
31	2.2 Subprogram bodies
33	2.3 Subprogram overloading
36	2.4 Resolution functions
37	2.5 Package declarations
38	2.6 Package bodies
39	2.7 Conformance rules
40	3. Types and natures
41	3.1 Scalar Types
47	3.2 Composite types
52	3.3 Access types
54	3.4 File types
57	3.5 Natures
60	4. Declarations 4.1 Type declarations
61	4.2 Subtype declarations
62	4.3 Objects
80	4.4 Attribute declarations
81	4.5 Component declarations 4.6 Group template declarations
82	4.7 Group declarations 4.8 Nature declaration
83	5. Specifications
84	5.1 Attribute specification
86	5.2 Configuration specification
93	5.3 Disconnection specification
95	5.4 Step limit specification
98	6. Names 6.1 Names
99	6.2 Simple names
100	6.3 Selected names
102	6.4 Indexed names 6.5 Slice names
103	6.6 Attribute names
104	7. Expressions 7.1 Rules for expressions
105	7.2 Operators
113	7.3 Operands
119	7.4 Static expressions
122	7.5 Universal expressions 7.6 Linear Forms
125	8. Sequential statements 8.1 Wait statement
127	8.2 Assertion statement
128	8.3 Report statement 8.4 Signal assignment statement
133	8.5 Variable assignment statement
134	8.6 Procedure call statement
135	8.7 If statement 8.8 Case statement
136	8.9 Loop statement
137	8.10 Next statement 8.11 Exit statement
138	8.12 Return statement 8.13 Null statement
139	8.14 Break statement
140	9. Concurrent statements 9.1 Block statement
141	9.2 Process statement
142	9.3 Concurrent procedure call statements
143	9.4 Concurrent assertion statements
144	9.5 Concurrent signal assignment statements
148	9.6 Component instantiation statements
154	9.7 Generate statements
155	9.8 Concurrent break statement
157	10. Scope and visibility 10.1 Declarative region 10.2 Scope of declarations
158	10.3 Visibility
161	10.4 Use clauses
162	10.5 �The context of overload resolution
164	11. Design units and their analysis 11.1 Design units 11.2 Design libraries
165	11.3 Context clauses
166	11.4 Order of analysis
167	12. Elaboration and execution 12.1 Elaboration of a design hierarchy
169	12.2 Elaboration of a block header
170	12.3 Elaboration of a declarative part
174	12.4 Elaboration of a statement part
177	12.5 Dynamic elaboration
178	12.6 Execution of a model
189	12.7 Time and the analog solver
190	12.8 Frequency and noise calculation
192	13. Lexical elements 13.1 Character set
195	13.2 Lexical elements, separators, and delimiters
196	13.3 Identifiers
197	13.4 Abstract literals
198	13.5 Character literals
199	13.6 String literals 13.7 Bit string literals
200	13.8 Comments
202	13.9 Reserved words
203	13.10 Allowable replacements of characters
204	14. Predefined language environment 14.1 Predefined attributes
225	14.2 Package STANDARD
231	14.3 Package TEXTIO
235	15. Simultaneous statements 15.1 Simple simultaneous statement
236	15.2 Simultaneous if statement 15.3 Simultaneous case statement
237	15.4 Simultaneous procedural statement
240	15.5 Simultaneous null statement
241	Annex A—Syntax summary
257	Annex B—Glossary
277	Annex C—Potentially nonportable constructs
278	Annex D—Changes from IEEE Std 1076-1987
279	Annex E—Bibliography
280	INDEX