IEEE 1076.3-1997

$86.13

IEEE Standard VHDL Synthesis Packages

Published By	Publication Date	Number of Pages
IEEE	1997

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Description

New IEEE Standard – Superseded. The current interpretation of common logic values and the association of numeric values to specific VHDL array types is described. This standard provides semantic for the VHDL synthesis domain, and enables formal verification and simulation acceleration in the VHDL based design. The standard interpretations are provided for values of standard logic types defined by IEEE Std 1164-1993, and of the BIT and BOOLEAN types defined in IEEE Std 1076-1993. The numeric types SIGNED and UNSIGNED and their associated operators define integer and natural number arithmetic for arrays of common logic values. Twos complement and binary encoding techniques are used. The numeric semantic is conveyed by two VHDL packages. This standard also contains any allowable modifications.

PDF Catalog

PDF Pages	PDF Title
1	Title Page
3	Introduction Participants
6	CONTENTS
7	1. Overview 1.1 Scope 1.2 Terminology
8	1.3 Conventions 2. References 3. Definitions
9	4. Interpretation of the standard logic types 4.1 The STD_LOGIC_1164 values
10	4.2 Static constant values 4.3 Interpretation of logic values
12	5. The STD_MATCH function 6. Signal edge detection 7. Standard arithmetic packages
14	7.1 Allowable modifications
15	7.2 Compatibility with IEEE Std 1076-1987 7.3 The package texts
45	Annex A—Notes on the package functions