IEEE 1076.6-1999
$80.71
IEEE Standard for VHDL Register Transfer Level Synthesis
| Published By | Publication Date | Number of Pages |
| IEEE | 1999 |
New IEEE Standard – Superseded. A standard syntax and semantics for VHDL register transfer level (RTL) synthesis is defined. The subset of IEEE 1076 (VHDL) that is suitable for RTL synthesis is defined, along with the semantics of that subset for the synthesis domain.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 1 | Title Page |
| 3 | Introduction Participants |
| 5 | CONTENTS |
| 7 | 1. Overview 1.1 Scope 1.2 Compliance to this standard |
| 8 | 1.3 Terminology 1.4 Conventions |
| 9 | 2. References 3. Definitions |
| 10 | 4. Predefined types |
| 11 | 5. Verification methodology 5.1 Combinational verification |
| 12 | 5.2 Sequential verification 6. Modeling hardware elements |
| 13 | 6.1 Edge-sensitive sequential logic |
| 17 | 6.2 Level-sensitive sequential logic |
| 18 | 6.3 Three-state and bus modeling 6.4 Modeling combinational logic 7. Pragmas 7.1 Attributes |
| 19 | 7.2 Metacomments |
| 20 | 8. Syntax 8.1 Design entities and configurations |
| 25 | 8.2 Subprograms and packages |
| 29 | 8.3 Types |
| 34 | 8.4 Declarations |
| 40 | 8.5 Specifications |
| 42 | 8.6 Names |
| 44 | 8.7 Expressions |
| 49 | 8.8 Sequential statements |
| 55 | 8.9 Concurrent statements |
| 60 | 8.10 Scope and visibility |
| 61 | 8.11 Design units and their analysis |
| 62 | 8.12 Elaboration 8.13 Lexical elements 8.14 Predefined language environment |
| 65 | Annex AāSyntax summary |
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