IEEE 1149.1 1990

$63.38

IEEE Standard Test Access Port and Boundary-Scan Architecture

Published By	Publication Date	Number of Pages
IEEE	1990	139

Guaranteed Safe Checkout

Category: IEEE

If you have any questions, feel free to reach out to our online customer service team by clicking on the bottom right corner. We’re here to assist you 24/7.
Email:[email protected]

Description

Revision Standard – Inactive – Superseded. Circuitry that may be built into an integrated circuit to assist in the test, maintenance, and support of assembled printed circuit boards is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards.

PDF Catalog

PDF Pages	PDF Title
1	Title Page
3	Foreword Participants
11	CONTENTS
13	1. Introduction 1.1 Background Reading 1.2 An Overview of the Operation of IEEE Std 1149.1
14	1.3 The Use of IEEE Std 1149.1 to Test an Assembled Product
17	1.4 The Use of IEEE Std 1149.1 to Achieve Other Test Goals 2. General Information 2.1 Document Outline
18	2.2 Conventions 2.3 Definitions
21	2.4 References 3. The Test Access Port (TAP) 3.1 Connections That Form the Test Access Port (TAP) 3.2 The Test Clock Input—TCK
22	3.3 The Test Mode Select Input—TMS
23	3.4 The Test Data Input—TDI 3.5 The Test Data Output—TDO
24	3.6 The Test Reset Input—TRST*
25	3.7 Interconnection of Components Compatible With This Standard
26	3.8 Subordination of This Standard Within a Higher Level Test Strategy
27	4. Test Logic Architecture
28	4.1 Test Logic Design
29	4.2 Test Logic Realization
30	5. The TAP Controller 5.1 TAP Controller State Diagram
35	5.2 TAP Controller Operation
43	5.3 TAP Controller Initialization
44	6. The Instruction Register 6.1 Design and Construction of the Instruction Register
45	6.2 Instruction Register Operation
47	7. Instructions 7.1 Response of the Test Logic to Instructions
48	7.2 Public Instructions
49	7.3 Private Instructions 7.4 The
50	7.5 Boundary-Scan Register Instructions
54	7.6 The
55	7.7 The
60	7.8 The
64	7.9 The
66	7.10 The
67	7.11 Device Identification Register Instructions 7.12 The
68	7.13 The
69	7.14 The
70	8. Test Data Registers
71	8.1 Provision of Test Data Registers
73	8.2 Design and Construction of Test Data Registers
74	8.3 Test Data Register Operation
76	9. The Bypass Register 9.1 Design and Operation of the Bypass Register
77	10. The Boundary-Scan Register
78	10.1 Introduction to This Chapter
82	10.2 Register Design
84	10.3 Register Operation
85	10.4 General Rules Regarding Cell Provision
88	10.5 Provision and Operation of Cells at System Logic Inputs
96	10.6 Provision and Operation of Cells at System Logic Outputs
111	10.7 Bidirectional Signals
116	10.8 Redundant Cells
117	10.9 Special Cases
119	11. The Device Identification Register
120	11.1 Design and Operation of the Device Identification Register
122	11.2 Manufacturer Identity Code
123	11.3 Part-Number Code 11.4 Version Code 12. Conformance and Documentation Requirements 12.1 Claiming Conformance to This Standard
124	12.2 Prime and Second Source Components
125	12.3 Documentation Requirements
128	Annex A An Example Implementation Using Level-Sensitive Design Techniques