IEEE 1149.1-2013(Redline)

$243.75

IEEE Standard for Test Access Port and Boundary-Scan Architecture (Redline)

Published By	Publication Date	Number of Pages
IEEE	2013

Guaranteed Safe Checkout

Category: IEEE

If you have any questions, feel free to reach out to our online customer service team by clicking on the bottom right corner. We’re here to assist you 24/7.
Email:[email protected]

Description

Revision Standard – Active. Circuitry that may be built into an integrated circuit to assist in the test, maintenance and support of assembled printed circuit boards and the test of internal circuits is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards. Also, a language is defined that allows rigorous structural description of the component-specific aspects of such testability features, and a second language is defined that allows rigorous procedural description of how the testability features may be used.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1149.1-2013 Front Cover
6	Notice to users Laws and regulations Copyrights Updating of IEEE documents Errata
7	Patents
8	Participants
10	Introduction History of the development of this standard
11	Changes introduced by this revision
14	Contents
19	Figures
22	Tables
23	Important Notice 1. Overview 1.1 Scope 1.2 Purpose 1.2.1 Overview of the operation of this standard
24	1.2.2 Use of this standard to test an assembled product
25	1.2.3 What is a boundary scan?
26	1.2.4 Use of this standard to achieve other test goals
27	1.3 Document outline 1.3.1 Specifications 1.3.2 Descriptions
28	1.4 Text conventions 1.5 Logic diagram conventions
29	2. Normative references
30	3. Definitions, abbreviations, acronyms, and special terms 3.1 Definitions
33	3.2 Abbreviations and acronyms
34	3.3 Special terms
35	4. Test access port (TAP) 4.1 Connections that form the TAP 4.1.1 Specifications Rules 4.1.2 Description 4.2 Test clock input (TCK) 4.2.1 Specifications Rules Recommendations
36	Permissions 4.2.2 Description 4.3 Test mode select (TMS) input 4.3.1 Specifications Rules Recommendations
37	4.3.2 Description 4.4 Test data input (TDI) 4.4.1 Specifications Rules 4.4.2 Description 4.5 Test data output (TDO)
38	4.5.1 Specifications Rules 4.5.2 Description 4.6 Test reset input (TRST*) 4.6.1 Specifications Rules
39	Recommendations 4.6.2 Description 4.7 Interconnection of components compatible with this standard 4.7.1 Specifications Permissions 4.7.2 Description
42	4.8 Subordination of this standard within a higher level test strategy 4.8.1 Specifications Rules
43	Recommendations Permissions 4.8.2 Description
44	5. Test logic architecture 5.1 Test logic design 5.1.1 Specifications Rules Permissions 5.1.2 Description
45	5.2 Test logic realization 5.2.1 Specifications Rules 5.2.2 Description
46	6. Test logic controllers 6.1 TAP controller 6.1.1 TAP controller state diagram 6.1.1.1 Specifications Rules
47	6.1.1.2 Description Test-Logic-Reset
48	Run-Test/Idle Select-DR-Scan Select-IR-Scan Capture-DR
49	Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR
50	Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR
51	Update-IR General
52	6.1.2 TAP controller operation 6.1.2.1 Specifications Rules
55	6.1.2.2 Description
60	6.1.3 TAP controller initialization 6.1.3.1 Specifications Rules 6.1.3.2 Description
61	6.2 Test mode persistence (TMP) controller 6.2.1 TMP controller state diagram 6.2.1.1 Specifications Rules
62	Recommendations 6.2.1.2 Description
64	6.2.2 TMP controller operation 6.2.2.1 Specifications Rules Permissions 6.2.2.2 Description
67	6.2.3 TMP controller initialization 6.2.3.1 Specifications Rules 6.2.3.2 Description
68	7. Instruction register 7.1 Design and construction of the instruction register 7.1.1 Specifications Rules Recommendations Permissions 7.1.2 Description
69	7.2 Instruction register operation 7.2.1 Specifications Rules
70	7.2.2 Description
72	8. Instructions 8.1 Response of the test logic to instructions 8.1.1 Specifications Rules Recommendations Permissions 8.1.2 Description
73	8.2 Public instructions 8.2.1 Specifications Rules Recommendations
74	Permissions 8.2.2 Description
75	8.3 Private instructions 8.3.1 Specifications Rules Permissions 8.3.2 Description 8.4 BYPASS instruction 8.4.1 Specifications Rules
76	Permissions Recommendations 8.4.2 Description 8.5 Boundary-scan register instructions 8.5.1 Overview of the operation of the boundary-scan register
78	8.5.2 Specifications for boundary-scan register instructions
79	8.6 SAMPLE instruction 8.6.1 Specifications Rules Recommendations Permissions 8.6.2 Description
80	8.7 PRELOAD instruction 8.7.1 Specifications Rules
81	Recommendations Permissions 8.7.2 Description
82	8.8 EXTEST instruction 8.8.1 Specifications Rules
83	Recommendations Permissions 8.8.2 Description
84	8.9 INTEST instruction
85	8.9.1 Specifications Rules Recommendations Permissions 8.9.2 Description
88	8.10 RUNBIST instruction 8.10.1 Specifications Rules
89	Recommendations Permissions 8.10.2 Description
90	8.11 CLAMP instruction
91	8.11.1 Specifications Rules Permissions 8.11.2 Description
92	8.12 Device identification register instructions 8.13 IDCODE instruction 8.13.1 Specifications Rules
93	Permissions 8.13.2 Description 8.14 USERCODE instruction 8.14.1 Specifications
94	Rules Permissions 8.14.2 Description
95	8.15 ECIDCODE instruction 8.15.1 Specifications Rules
96	Recommendations Permissions 8.15.2 Description 8.16 HIGHZ instruction 8.16.1 Specifications Rules
97	Permissions 8.16.2 Description
98	8.17 Component initialization instructions and procedures 8.17.1 Specifications Rules
99	Permissions Recommendations 8.17.2 Description
103	8.18 INIT_SETUP and INIT_SETUP_CLAMP instructions 8.18.1 Specifications Rules
104	Permissions 8.18.2 Description 8.19 INIT_RUN instruction 8.19.1 Specifications Rules
105	Recommendations Permissions 8.19.2 Description
106	8.20 CLAMP_HOLD, CLAMP_RELEASE, and TMP_STATUS instructions 8.20.1 Specifications Rules
107	Permissions 8.20.2 Description
110	8.21 IC_RESET instruction 8.21.1 Specifications Rules
111	Recommendations Permissions 8.21.2 Description
113	9. Test data registers 9.1 Provision of test data registers 9.1.1 Specifications Rules
114	Permissions Recommendations 9.1.2 Description Bypass register
115	Boundary-scan register 9.1.2.1 Optional standard test data registers Device identification register Electronic chip identification register Initialization data register Initialization status register TMP status register Reset selection register 9.1.2.2 Design-specific test data registers
116	9.2 Design and construction of test data registers 9.2.1 Specifications Rules Permissions Recommendations
117	9.2.2 Description
118	9.2.3 TAP-to-TDR interface
119	9.2.4 Test data register cell design examples
120	Gated-clock example TDR bit Ungated-clock example TDR bits
128	9.3 Operation of test data registers 9.3.1 Specifications Rules Permissions
129	Recommendations 9.3.2 Description
130	9.4 Design and control of test data register segments
131	9.4.1 Specifications Rules
133	Permissions Recommendations 9.4.2 Description Excludable segments
136	Selectable segments
138	10. Bypass register 10.1 Design and operation of the bypass register 10.1.1 Specifications Rules 10.1.2 Description
140	11. Boundary-scan register 11.1 Introduction 11.1.1 Approach
142	11.1.2 Signal paths to the on-chip system logic 11.1.3 Boundary-scan register cell
144	11.2 Register design 11.2.1 Specifications Rules
145	Permissions
146	11.2.2 Description 11.3 Register operation 11.3.1 Specifications Rules
147	Permissions
148	11.3.2 Description 11.4 General rules regarding cell provision 11.4.1 Specification Rules
149	Permissions 11.4.2 Description
153	11.5 Provision and operation of cells at system logic inputs 11.5.1 Specifications Rules
156	Permissions
157	11.5.2 Description
160	11.6 Provision and operation of cells at system logic outputs
161	11.6.1 Specifications Rules
166	Recommendations Permissions
167	11.6.2 Description
176	11.7 Provision and operation of cells at bidirectional system logic pins 11.7.1 Specifications Rules 11.7.2 Description
183	11.8 Redundant cells
184	11.8.1 Specifications Rules Permissions Recommendations 11.8.2 Description
185	11.9 Special cases 11.9.1 Specifications Permissions 11.9.2 Description
188	12. Device identification register 12.1 Design and operation of the device identification register 12.1.1 Specifications Rules 12.1.2 Description
190	12.2 Manufacturer identity code 12.2.1 Specifications Rules Recommendations 12.2.2 Description
191	12.3 Part-number code 12.3.1 Specifications Rules Recommendations Permissions 12.3.2 Description
192	12.4 Version code 12.4.1 Specifications Rules Recommendations Permissions 12.4.2 Description
193	13. Electronic chip identification (ECID) register 13.1 Design and operation of the ECID register 13.1.1 Specifications Rules Permissions 13.1.2 Description
194	14. Initialization data register 14.1 Design and operation of the initialization data register 14.1.1 Specifications Rules Recommendations Permissions
195	14.1.2 Description
197	15. Initialization status register 15.1 Design and operation of the initialization status register 15.1.1 Specifications Rules Recommendations 15.1.2 Description
198	16. TMP status register 16.1 Design and operation of the TMP status register 16.1.1 Specifications Rules 16.1.2 Description
200	17. Reset selection register 17.1 Design and operation of the reset selection register
201	17.1.1 Specifications Rules Permissions
202	17.1.2 Description
205	18. Conformance and documentation requirements 18.1 Claiming conformance to this standard 18.1.1 Specifications Rules Recommendations Permissions 18.1.2 Description
206	18.2 Prime and second source components 18.2.1 Specifications Rules 18.2.2 Description 18.3 Documentation requirements 18.3.1 Specifications Rules
208	18.3.2 Description
210	Annex A (informative) Example implementation using level-sensitive design techniques
211	Annex B (normative) Boundary Scan Description Language (BSDL) B.1 General information B.1.1 Document outline B.1.2 Conventions B.1.3 BSDL history
212	B.2 Purpose of BSDL B.3 Scope of BSDL
213	B.4 Relationship of BSDL to VHDL B.4.1 Specifications
214	Rules Permissions B.5 Lexical elements of BSDL B.5.1 Character set B.5.1.1 Specifications Rules
215	B.5.2 BSDL reserved words B.5.2.1 Specifications Rules
216	B.5.3 VHDL reserved and predefined words
217	B.5.3.1 Specifications Rules B.5.4 Identifiers B.5.4.1 Specifications Rules
218	B.5.5 Numeric literals B.5.5.1 Specifications Rules
219	B.5.5.2 Description B.5.6 Strings B.5.6.1 Specifications Rules
220	B.5.6.2 Description B.5.7 Information tag B.5.7.1 Specifications Rules B.5.7.2 Description
221	B.5.8 Comments B.5.8.1 Specifications Rules B.6 Syntax definition B.6.1 BNF conventions
222	B.6.2 Commonly used syntactic elements B.6.2.1 Specifications Syntax
223	Rules
224	B.7 Components of a BSDL description B.7.1 Specifications Rules
225	Permissions B.7.2 Description B.8 Entity description B.8.1 Overall syntax of the entity description B.8.1.1 Specifications Syntax
226	Rules Recommendations B.8.2 Generic parameter statement
227	B.8.2.1 Specifications Syntax Rules B.8.2.2 Description B.8.2.3 Examples B.8.3 Logical port description statement B.8.3.1 Specifications Syntax
228	Rules Permissions B.8.3.2 Description
230	B.8.3.3 Example B.8.4 Standard use statement
231	B.8.4.1 Specifications Syntax Rules B.8.4.2 Description
232	B.8.4.3 Examples B.8.4.4 Version control
233	B.8.5 Use statement B.8.5.1 Specifications Syntax Rules
234	B.8.5.2 Description B.8.5.3 Example B.8.6 Component conformance statement B.8.6.1 Specifications Syntax
235	Rules B.8.6.2 Description B.8.6.3 Example B.8.7 Device package pin mappings B.8.7.1 Specifications Syntax
236	Rules Permissions B.8.7.2 Examples
237	B.8.7.3 Description
238	B.8.8 Grouped port identification
239	B.8.8.1 Specifications Syntax Rules
240	B.8.8.2 Description B.8.8.3 Examples
241	B.8.9 Scan port identification B.8.9.1 Specifications Syntax Rules
242	B.8.9.2 Description Examples B.8.10 Compliance-enable description B.8.10.1 Specifications Syntax Rules
243	Permissions B.8.10.2 Description B.8.10.3 Examples B.8.11 Instruction register description
244	B.8.11.1 Specifications Syntax Rules
245	B.8.11.2 Description
246	B.8.11.3 Examples B.8.12 Optional device register description
247	B.8.12.1 Specifications Syntax Rules Recommendations Permissions B.8.12.2 Description
248	B.8.12.3 Examples
249	B.8.13 Register access description B.8.13.1 Specifications Syntax Rules
250	B.8.13.2 Examples B.8.13.3 Description
251	B.8.14 Boundary-scan register description
253	B.8.14.1 Specifications Syntax
254	Rules
257	Permissions B.8.14.2 Examples Example 1
258	Example 2
259	B.8.14.3 Description
260	B.8.14.3.1 element B.8.14.3.2 element B.8.14.3.3 element
262	B.8.14.3.4 element B.8.14.3.5 element B.8.14.3.6 element B.8.14.3.7 element
263	B.8.14.3.8 element
267	B.8.15 RUNBIST description
268	B.8.15.1 Specifications Syntax Rules
269	B.8.15.2 Examples B.8.16 INTEST description
270	B.8.16.1 Specifications Syntax Rules B.8.16.2 Examples
271	B.8.17 System clock requirements attribute B.8.17.1 Specifications Syntax Rules
272	B.8.17.2 Description B.8.17.3 Examples B.8.18 Register mnemonics description B.8.18.1 Specifications Syntax
273	Rules B.8.18.2 Description
274	B.8.18.3 Examples Example 1 Example 2
275	Example 3
276	B.8.19 Register fields description
277	B.8.19.1 Specifications Syntax
278	Rules B.8.19.2 Description
280	B.8.19.3 Examples
283	B.8.20 Register field assignment description
284	B.8.20.1 Specifications Syntax Rules
286	Recommendations
287	B.8.20.2 Description
293	B.8.21 Register assembly description B.8.21.1 Specifications Syntax
294	Rules
297	Permissions Recommendations B.8.21.2 Description
300	Excludable register segments and domain control
301	Selectable register segments
303	B.8.21.3 Examples Initialization REGISTER_ASSEMBLY example
305	Boundary-scan example Power-domain control example
307	IEEE 1500 WSP Examples
310	B.8.22 Register constraint description B.8.22.1 Specifications Syntax
311	Rules
312	B.8.22.2 Description
313	B.8.22.3 Examples B.8.23 Register and power port association attributes B.8.23.1 Specifications Syntax
314	Rules
315	B.8.23.2 Description
316	B.8.23.3 Examples
317	B.8.24 User extensions to BSDL B.8.24.1 Specifications Syntax Rules
318	Permissions B.8.24.2 Description B.8.24.3 Examples
319	B.8.25 Design warning B.8.25.1 Specifications Syntax B.8.25.2 Description B.8.25.3 Examples
320	B.9 Standard BSDL Package STD_1149_1_2013
324	B.10 User-supplied BSDL packages B.10.1 Specifications Syntax
325	Rules
327	Recommendations
328	B.10.2 Description
329	B.10.3 Examples User-supplied package for boundary-register cells
330	User-supplied package body for internal registers B.11 BSDL example applications B.11.1 Typical application of BSDL
333	B.11.2 Boundary-scan register description B.11.2.1 Multiple cells per pin
335	B.11.2.2 Internal boundary register cells
336	B.11.2.3 Merged cells
337	B.12 1990 version of BSDL
338	B.12.1 1990 Standard VHDL Package STD_1149_1_1990
341	B.12.2 Typical application of BSDL, 1990 version
342	B.12.3 Obsolete syntax
343	B.12.3.1 Syntax B.12.4 Miscellaneous points on 1990 version B.13 1994 version of BSDL B.13.1 Standard VHDL Package STD_1149_1_1994
347	B.14 2001 version of BSDL B.14.1 Standard VHDL Package STD_1149_1_2001
351	Annex C (normative) Procedural Description Language (PDL) C.1 General information C.1.1 Purpose
352	C.1.2 Dependence on Tool Command Language (Tcl) C.1.3 Dependence on Boundary Scan Description Language (BSDL) C.2 PDL concepts and use model C.2.1 Use model introduction
354	C.2.2 PDL levels C.2.2.1 Level-0 PDL
355	C.2.2.2 Level-1 PDL C.2.3 PDL procedures
356	C.2.4 Read and write with capture-shift-update sequence C.2.5 Register state definition
358	C.2.6 Level-0 PDL commands
361	C.2.7 Specification of names and values
362	C.2.8 Retargeting
363	C.2.9 Simple PDL Example U3.PDL
364	MEMB.PDL Chip_A.PDL
365	C.3 PDL Level 0 command reference C.3.1 Understanding a PDL “string”
366	C.3.2 BNF conventions
367	C.3.3 PDL lexical elements and common syntax C.3.3.1 Lexical element specifications General rules
368	Numeric literal rules
369	Identifier rules Text string rules C.3.3.2 Substitutions
370	Rules
371	C.3.3.3 Common syntax Syntax Rules Description
372	C.3.3.4 PDL reserved words Rules Recommendations C.3.4 PDL File Syntax Rules
373	Permissions C.3.5 Procedure definition commands C.3.5.1 iSource command Syntax Rules Example C.3.5.2 iPDLLevel command
374	Syntax Rules Permissions Example C.3.5.3 iProcGroup command
375	Syntax Rules Permissions Example C.3.5.4 iProc command
376	Syntax Rules
377	Predefined procedure names
378	C.3.6 Test setup commands C.3.6.1 iPrefix command Syntax
379	Rules Examples C.3.6.2 iSetInstruction command Syntax Rules
380	Examples C.3.6.3 iClock and iClockOverride commands Syntax Rules
381	Examples
382	C.3.7 Test execution commands C.3.7.1 iRead and iWrite commands Syntax Rules
383	Examples
384	C.3.7.2 iApply command
386	Syntax Rules
387	Recommendations Examples
388	C.3.7.3 iScan command Syntax
389	Rules Examples C.3.8 Flow-control commands C.3.8.1 iCall command
390	Syntax Rules Examples
391	C.3.8.2 iRunLoop command Syntax
392	Rules Recommendations Examples
393	C.3.8.3 iLoop and iUntil commands Syntax Rules
394	Example A Example B C.3.8.4 ifTrue, ifFalse and ifEnd commands
395	Syntax Rules Example A
396	Example B C.3.9 Optimization commands C.3.9.1 iMerge command
397	Syntax Rules Example
398	C.3.9.2 iTake and iRelease commands
399	Syntax Rules Example
400	C.3.10 Miscellaneous commands C.3.10.1 iNote command Syntax Recommendations Example A
401	Example B C.3.10.2 iSetFail command Syntax Rules Recommendations Examples C.3.11 Low-level commands
402	C.3.11.1 iTMSreset and iTRST commands Syntax Rules
403	Recommendations Example C.3.11.2 iTMSidle command Syntax Rules Examples
404	C.4 PDL Level 1 command reference
405	C.4.1 Level-1 PDL operation C.4.2 iGet command
406	Syntax Rules
407	Example A Example B
408	Example C Example D Example E
409	Example F Example G
410	C.4.3 iGetStatus command Syntax Rules Example C.5 Example BSDL and PDL for the use model
411	C.5.1 BSDL Packages for IP MEMB
412	SERDES C.5.2 BSDL files for components Chip_A
413	Chip_B
414	Chip_C
415	C.5.3 PDL files supplied by IP supplier MEMB SERDES
416	C.5.4 PDL files supplied by component supplier Chip_A
417	Chip_B Chip_C C.5.5 PDL files coded by test engineer U1 U2
418	U3 U4 UUT
420	Annex D (informative) Integrated examples of BSDL and PDL D.1 Initialization example structure and procedures D.1.1 Initialization example using register description attributes
427	D.1.2 Example PDL for INIT example
430	D.2 Multiple wrapper serial port structure and procedures D.2.1 Wrapper serial port structural description Single WSP
432	Multiple selectable and gated WSP
439	D.2.2 Wrapper serial port example Reg_1500.pdl Reg_1500S.pdl Reg_1500_Assm.pdl
442	Annex E (informative) Example iApply execution flow