IEEE 1149.4-1999

$79.08

IEEE Standard for a Mixed-Signal Test Bus

Published By	Publication Date	Number of Pages
IEEE	1999

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Description

New IEEE Standard – Superseded. The testability structure for digital circuits described in IEEE Std 1149.1-1990 has been extended to provide similar facilities for mixed-signal circuits. The architecture is described, together with the means of control of and access to both analog and digital test data. Sample implementation and application details (which are not part of the standard) are included for illustration.

PDF Catalog

PDF Pages	PDF Title
1	Title Page
3	Introduction Participants
5	CONTENTS
7	1. Overview 1.1 Organization of the standard 1.2 Context
8	1.3 Scope of the standard
11	1.4 Background reading 2. References
12	3. Definitions, acronyms, and voltage symbols 3.1 Definitions
15	3.2 Acronyms
16	3.3 Voltage source symbols 4. Testability architecture 4.1 Overview
18	4.2 TAP controller
19	4.3 ATAP 4.4 Register architecture
21	5. Instructions 5.1 General 5.2 Response of test logic to instructions
22	5.3 Mandatory instructions
24	5.4 Optional instructions
29	6. The TBIC 6.1 General
30	6.2 Test bus and TBIC structure
34	6.3 Control of the TBIC
37	6.4 Differential I/O 6.5 Partitioned internal test bus structure
41	7. The boundary-scan structure 7.1 Structure
42	7.2 DBMs
44	7.3 ABMs
53	7.4 Differential ABMs
58	8. Measurement methodology 8.1 Interconnect testing
61	8.2 Extended interconnect testing
65	8.3 Network measurements
66	9. Analog parametric limits 9.1 General 9.2 Switch limitations
67	9.3 Electrostatic protection
68	9.4 Performance specifications
70	9.5 Measuring performance
76	9.6 Calibration and errors
79	10. Conformance and documentation 10.1 Conformance 10.2 General documentation
83	10.3 Documentation of residual elements