New IEEE Standard – Inactive – Withdrawn. This Standard specifies a serial, backplane, test and maintenance bus (MTM-Bus) that can be used to integrate modules from different design teams or vendors into testable and maintainable subsystems. Physical, link, and command layers are specified. Standard interface protocol and commands can be used to provide the basic test and maintenance features needed for a module as well as access to on-module assets (memory, peripherials, etc.) and IEEE Std 1149.1 boundary-scan. Standard commands and functions support fault isolation to individual modules and test of backplane interconnect between modules. You will receive an email from Customer Service with the URL needed to access this publication online.

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PDF Pages	PDF Title
1	Title Page
3	Introduction Particpation
6	CONTENTS
10	1. Overview 1.1 Scope and objectives
11	1.2 The interconnection of modules with MTM-Bus
12	1.3 Relationship to other test buses 1.4 Overview of MTM-Bus operation/protocol
14	1.5 MTM-Bus protocol layers
15	1.6 Extensions to this Standard
18	2. Conventions, definitions, and references 2.1 Document outline 2.2 Conventions
19	2.3 Definitions
27	2.4 References
28	3. MTM-Bus architecture 3.1 MTM-Bus signals and interconnection of MTM-Bus modules via these signals
29	3.2 General architecture and MTM-Bus mastership
30	3.3 S-Module addressing requirements
34	4. MTM-Bus Physical Layer requirements 4.1 Physical layer requirements independent of module type
35	4.2 M-module Physical Layer requirements
36	4.3 S-Module Physical Layer requirements
37	4.4 MTM-Bus timing requirements
44	5. MTM-Bus Link Layer: Packet requirements 5.1 Requirements applicable to all packets 5.2 HEADER packet requirements
45	5.3 ACKNOWLEDGE packet requirements
46	5.4 PACKET COUNT packet requirements
47	5.5 DATA packet requirements
48	5.6 NULL packet requirements 5.7 Formatting bit strings of more than 16 bits for transmission in DATA packets
50	6. MTM-Bus Link Layer: M-Module requirements 6.1 MTM-Bus Master Link Layer Controller (M-Controller) requirements
58	6.2 M-module send and receive parity requirements
59	6.3 M-module MPR signal (data transfer control) requirements
60	6.4 M-module response to collision errors on MMD and MCTL signals 6.5 M-module interrupt response requirements
62	7. MTM-Bus Link Layer: S-module requirements—MTM-Bus Slave Link Layer Controller 7.1 MTM-Bus Slave Link Layer Controller requirements
69	7.2 S-module interface logic requirements
70	8. MTM-Bus Link Layer: S-module requirements—general communications 8.1 S-module send and receive parity requirements 8.2 S-module MSD signal general requirements
71	8.3 S-module MTM-Bus Pause Request (MPR) signal implementation (data transfer control) requirements
74	9. MTM-Bus Link Layer: S-module requirements—status registers 9.1 S-module status registers—general requirements
75	9.2 Slave Status register
80	9.3 Bus Error register
88	9.4 Module Status register
89	9.5 Additional status registers
92	10. MTM-Bus Link Layer: S-module interrupt generation 10.1 Interrupt generation other than immediate response to a State Sequence Error
96	11. S-module error response requirements 11.1 S-module error response—general requirements
98	11.2 S-module self-test failure response requirements
99	11.3 Broadcast and multicast errors
100	11.4 S-module Data Overrun Error and response requirements 11.5 S-module Parity Error response requirements
101	11.6 S-module State Sequence Error response requirements
103	11.7 MSD signal collision response requirements
104	11.8 S-module Data Transfer Port Error response requirements
105	11.9 S-module Command Sequence Error response requirements
106	11.10 S-module Illegal Command Error response requirements
107	11.11 S-module Packet Count Error response requirements
108	11.12 S-module Command Resource Unavailable Error response requirements
110	12. MTM-Bus Message Layer: General requirements 12.1 MTM-Bus Message Layer general requirements
114	13. MTM-Bus Message Layer: M-module requirements 13.1 M-module PACKET COUNT packet transmission requirements 13.2 Post-error recovery at packet and message levels
116	14. MTM-Bus Message Layer: S-module requirements 14.1 S-module general HEADER packet decode and general command response
117	14.2 S-module packet-counting requirements
118	14.3 Summary of S-module message sequence requirements
124	15. MTM-Bus Message Layer: Commands—general requirements 15.1 MTM-Bus commands—general requirements on command codes and command classes
127	15.2 Commands execution of which may be terminated upon receipt of another command
128	16. MTM-Bus Message Layer: Core Class commands (0000000-0011111; 1111111) 16.1 The Read Status command (0000000)
131	16.2 Abort command (0000001)
132	16.3 Reset Slave Status command (0000010)
133	16.4 Contend for Bus command (0000011)
136	16.5 Multicast Select n commands ( n = 0, 1, 2, 3) (0000100–0000111)
138	16.6 Enable Idle Interrupts command (0001000) 16.7 Enable Pause Interrupts command (0001001)
139	16.8 Disable Idle Interrupts command (0001010)
140	16.9 Disable Pause Interrupts command (0001011) 16.10 Enable Module Control (EMC) command (0001100)
142	16.11 Data Echo Test command (0001101)
143	16.12 Verify BMR command (0001110)
145	16.13 The Initialize Application command (0001111)
146	16.14 Disable Module Control command (0010000)
147	16.15 Start command (0010001)
148	16.16 Reserved commands (0010010–0011111) 16.17 Illegal command (1111111)
150	17. MTM-Bus Message Layer: Data Transfer class commands (010000-0100111) 17.1 General format requirements for Data Transfer class commands
151	17.2 Read Data command (0100000)
153	17.3 Write Data command (0100001)
154	17.4 Read/Write Data command (0100010)
156	17.5 Reserved commands (0100011–0100111)
158	18. MTM-Bus Message Layer: Module Initialization and Self-Test (MIST) class commands (0101000—0101111)
159	18.1 General requirements for MIST commands 18.2 Reset Module With Start-up Built-in Test (SBIT) command (0101000)
161	18.3 Reset Module Without SBIT command (0101001)
162	18.4 Module Initiated Built-In Test (Module IBIT) command (0101010)
164	18.5 Reserved commands (0101011–0101111)
166	19. MTM-Bus Message Layer: Module I/O Control and Test (MICT) class commands (0110000—0110111)
167	19.1 MICT class commands—general requirements
169	19.2 Disable Module I/O command (0110000)
171	19.3 Enable Module I/O command (0110001)
172	19.4 Force Module Outputs command (0110010)
174	19.5 Sample Module Inputs commands (0110011–0110101)—general requirements
176	19.6 Sample Module No Change command (0110011) 19.7 Sample Module Don’t Care command (0110100)
177	19.8 Sample Module With Force command (0110101)
178	19.9 Release Module I/O command (0110110)
179	19.10 Reserved commands (0110111–1001111)
180	20. MTM-Bus Message Layer: Standard Extension class commands and User-Defined class commands 20.1 Standard Extension class commands (1010000–1011111) 20.2 User-Defined class commands (1100000–1111110)
182	21. Data transfer ports 21.1 Data transfer ports—general requirements
184	21.2 Port definition and documentation requirements 21.3 Module/Fault log port(s) (‘0000’ HEX – ‘0003’ HEX)
185	21.4 Test Data Storage ports (‘0004’ HEX – ‘0007’ HEX)
186	21.5 Error/Status register ports (‘0008’ HEX – ‘000B’ HEX)
187	21.6 MTM-Bus Interface Manufacturer ID port (‘000C’ HEX)
189	21.7 Module Manufacturer port (‘000D’ HEX)
191	21.8 User Identification ports (‘000E’ HEX – ‘000F’ HEX)
192	21.9 Access to status register backup means—Error/Status Shadow register port (‘0080’ HEX)
193	21.10 Ports interfacing to IEEE Std 1149.1 boundary-scan (‘0010′ HEX – ‘001F’ HEX)
200	21.11 IEEE Std 1149.1 Interface ports—requirements for the Full TAP Control (FTC) access method
206	21.12 IEEE Std 1149.1 Interface ports—requirements for the Function-Based Control (FBC) access method
216	22. MTM-Bus general documentation requirements 22.1 Documentation requirements

Published By	Publication Date	Number of Pages
IEEE	1996	217


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Standard Title	IEEE Standard for Module Test and Maintenance Bus (MTM-Bus) Protocol
Published Code	IEEE
Publication Date	1996
Pages Count	217

IEEE 1149.5 1996

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