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IEEE 1149.7-2009

IEEE 1149.7-2009

$208.54

IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture (Inactive Reserved)

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IEEE 2009
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New IEEE Standard – Inactive-Reserved. This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0-T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.

PDF Catalog

PDF Pages PDF Title
1 IEEE Std 1149.7-2009 Front Cover
3 Title Page
6 Introduction
Notice to users
Laws and regulations
7 Copyrights
Updating of IEEE documents
Errata
Interpretations
Patents
8 Participants
9 Contents
36 Figures
47 Tables
53 Important Notice
1. Overview
1.1 Scope
1.2 Purpose
54 1.3 Contrasting IEEE Std 1149.1-2001 and this standard
55 1.4 Challenges
56 1.5 Important considerations
1.6 Nomenclature
58 1.7 Ensuring transparency to IEEE 1149.1 intellectual property
59 1.8 Maximizing compatibility with 1149.1 IP
62 1.9 Scalability
64 1.10 Flexibility
66 1.11 Document content
67 1.12 Document organization
71 1.13 Using the standard
72 1.14 Conventions
78 2. Normative references
79 3. Definitions, acronyms, and abbreviations
3.1 Definitions
83 3.2 Acronyms and abbreviations
88 4. TAP.7 concepts and architecture
4.1 Introduction
4.2 Concepts supporting system architecture
103 4.3 Concepts supporting pin efficiency
111 4.4 Concepts supporting capability
112 4.5 IEEE 1149.7 architecture
117 4.6 Operating models
120 5. T0ā€“T3 TAP.7 operational overview
5.1 Introduction
5.2 T0 TAP.7
124 5.3 T1 TAP.7
134 5.4 T2 TAP.7
141 5.5 T3 TAP.7
153 6. T4ā€“T5 TAP.7 operational overview
6.1 Introduction
154 6.2 T4 TAP.7
163 6.3 T5 TAP.7
172 6.4 TAP.7 feature summary
174 7. System concepts
7.1 Introduction
7.2 Key system attributes
7.3 DTS/TS connectivity with a mix of technologies
176 7.4 TAP.7 deployment scenarios
177 7.5 Chip TAPC hierarchy
178 7.6 Combined view of TAP connectivity and TAPC hierarchy
179 7.7 Chips, components, and boards
181 8. TAPC hierarchy
8.1 Introduction
8.2 Selection/deselection with the TAPC hierarchy
182 8.3 TAPC selection/deselection characteristics
184 8.4 ADTAPC selection/deselection
186 8.5 CLTAPC selection/deselection
188 8.6 EMTAPC selection/deselection
189 8.7 Using a common selection/deselection protocol across technologies
8.8 RSU deployment
190 8.9 Using the TAPC hierarchy
191 8.10 Test/debug applications and the TAPC hierarchy
194 9. Registers, commands, and scan paths
9.1 Introduction
9.2 Command basics
196 9.3 Register portfolio
199 9.4 Command portfolio
206 9.5 Representation of commands in examples
9.6 Global and Local Register programming with commands
207 9.7 1Scan paths
218 9.8 Two-part commands
9.9 Three-part commands
222 9.10 RDBACKx and CNFGx Registers
228 9.11 An approach to implementing command processing and scan paths
232 10. RSU ancillary services
10.1 Introduction
10.2 Resets
239 10.3 Start-up options
247 10.4 Escape Detection
253 10.5 Selection Alert
259 10.6 Deselection Alert
260 10.7 Programming considerations
261 10.8 ADTAPC State Machine
263 11. RSU Online/Offline capability
11.1 Introduction
11.2 Managing Online/Offline operation
264 11.3 Online/Offline operating principles
267 11.4 Initiating Offline operation
269 11.5 Initiating Online operation
270 11.6 Context-sensitive response to Selection and Deselection Escapes
273 11.7 Selection Sequence
284 11.8 Parking-state considerations
287 11.9 Control State Machine
310 11.10 Programming considerations
314 12. TAP signals
12.1 Introduction
12.2 TAP.7 Class/signal relationships
316 12.3 Signal function and bias
318 12.4 Test Reset (nTRST and nTRST_PD) signals
319 12.5 TAP.7 signal functions with corresponding IEEE 1149.1 names
12.6 Test Clock (TCK)
320 12.7 Test Mode Select (TMS/TMSC)
327 12.8 Test Data Input (TDI/TDIC)
330 12.9 Test Data Output (TDO/TDOC)
332 12.10 Offline-at-Start-up behavior
333 12.11 TAP connections
334 12.12 Applicability of this standard
335 12.13 Recommendations for interoperability
338 13. TDO(C) Signal Drive Policy
13.1 Introduction
13.2 TDO(C) Signal Drive Types
340 13.3 Factors affecting the TDO(C) Drive Policy
341 13.4 TDO(C) Drive Policy template
348 13.5 T0 TAP.7 TDOC Drive Policy
349 13.6 T1 and T2 TAP.7 TDOC Drive Policy
351 13.7 T3 and above TAP.7 TDOC Drive Policy
354 13.8 STL Group Membership
368 13.9 EPU Group Membership
372 13.10 Drive Policy summary
373 13.11 An approach to implementing TDOC Drive Policy
376 13.12 Programming considerations
377 14. TMS(C) Signal Drive Policy
14.1 Introduction
14.2 TMS(C) output bit types
380 14.3 Drive policy by output bit type
381 14.4 TMSC Signal Drive Types
383 14.5 Dormant Bit Drive Policy
14.6 Precharge Bit Drive Policy
384 14.7 RDY Bit Drive Policy
387 14.8 TDO Bit Drive Policy
391 14.9 Transport Bit Drive Policy
392 14.10 An approach to implementing TMSC Drive Policy
396 14.11 Programming considerations
398 15. IEEE 1149.1-compliance concepts
15.1 Introduction
15.2 Background
399 15.3 Test and debug views of a system of interest
400 15.4 An approach to implementing EMTAPC selection/deselection
401 16. T0 TAP.7
16.1 Introduction
16.2 Deployment
402 16.3 Capabilities
16.4 Configurations
403 16.5 Start-up behavior
16.6 Supporting multiple on-chip TAPCs
404 16.7 Controlling the selection state of EMTAPCs
407 16.8 Control via the CLTAPC Instruction Register
411 16.9 Control via one or more CLTAPC Data Registers
413 16.10 Control via internal or external tapc_select signals
415 16.11 Example use cases
418 16.12 Identification of on-chip TAP controller(s)
419 16.13 Multiple dies in one package
424 16.14 Managing STL Group Membership
16.15 RSU operation
425 16.16 Programming considerations
426 17. Extended concepts
17.1 Introduction
17.2 Suitability of BYPASS and IDCODE instructions for extended control
17.3 ZBS detection
427 17.4 Incrementing, locking, and clearing the ZBS count
430 17.5 Shared use of ZBSs by the EPU and STL
436 17.6 EPU functionality associated with the ZBS count
437 17.7 Programming considerations
438 18. T1 TAP.7
18.1 Introduction
439 18.2 Deployment
18.3 Capabilities
440 18.4 Register and command portfolio
444 18.5 Configurations
445 18.6 Start-up behavior
18.7 Conditional Group Membership
446 18.8 Test Reset
448 18.9 Functional reset
452 18.10 Power control
473 18.11 RSU operation
474 18.12 Programming considerations
475 19. T2 TAP.7
19.1 Introduction
477 19.2 Deployment
19.3 Capabilities
478 19.4 Register and command portfolio
480 19.5 Configurations
19.6 Start-up behavior
481 19.7 Scan formats
19.8 STL Group Membership
490 19.9 RSU operation
491 19.10 Programming considerations
492 20. T3 TAP.7
20.1 Introduction
494 20.2 Deployment
495 20.3 Capabilities
20.4 Register and command portfolio
497 20.5 Configurations
498 20.6 Start-up behavior
20.7 Scan formats
499 20.8 TAP.7 Controller Address (TCA)
501 20.9 Aliasing the TCA to a Controller ID
509 20.10 Scan Selection Directives
528 20.11 Scan Topology Training Sequence
533 20.12 Managing STL Group Membership
537 20.13 RSU operation
538 20.14 Programming considerations
539 21. Advanced concepts
21.1 Architecture
540 21.2 Advanced capabilities
542 21.3 Comparing the Standard and Advanced Protocols
21.4 APU functions
547 21.5 APU interfaces
550 21.6 APU function/Operating State relationships
554 21.7 TAPC state/packet relationships
559 21.8 Userā€™s and implementerā€™s views of the Advanced Protocol
560 21.9 An approach to implementing APU Operating State scheduling
562 21.10 Structure of the clauses describing T4 and above TAP.7s
564 22. APU Scan Packets
22.1 CPs
22.2 SPs
569 22.3 SPs that advance the TAPC state
570 22.4 TPs
572 22.5 APU state diagram
574 22.6 An approach to implementing packet scheduling
576 23. T4 TAP.7
23.1 Introduction
23.2 Deployment
577 23.3 Capabilities
578 23.4 Register and command portfolio
582 23.5 Configurations
583 23.6 Start-up behavior
584 23.7 Scan formats
588 23.8 Configuration Faults
589 23.9 Increasing STL performance
592 23.10 Auxiliary Pin Function Control
593 23.11 Sample Using Rising Edge
594 23.12 System and EPU TMS signal values
596 23.13 System and EPU TDI signal values
598 23.14 RDY bit values
600 23.15 TDO bit values
601 23.16 Advanced Protocol effects on the EPU/CLTAPC relationship
23.17 SSD detection
602 23.18 Programming considerations
23.19 An approach to implementing a TAP.7 Controller with maximumperformance
604 24. MScan Scan Format
24.1 Capabilities
605 24.2 High-level operation
606 24.3 Scan Packet content
24.4 Payload Element
611 24.5 Delay Element
614 24.6 Advancing the TAPC state
24.7 CID allocation
616 24.8 Increasing STL performance with the MScan Scan Format
24.9 An approach to implementing the MScan Scan Format
620 24.10 Where to find examples
621 25. OScan Scan Formats
25.1 Capabilities
622 25.2 High-level operation
623 25.3 Scan Packet content
624 25.4 Payload Element
633 25.5 Delay Element
634 25.6 Advancing the TAPC state
636 25.7 CID allocation
637 25.8 Increasing STL performance with OScan Scan Formats
25.9 An approach to implementing OScan Scan Formats
641 25.10 Where to find examples
642 26. SScan Scan Formats
26.1 Capabilities
646 26.2 High-level operation
651 26.3 Scan Packet content
653 26.4 Header Element
654 26.5 Payload Element
669 26.6 Delay Element
670 26.7 Packet sequences and factors influencing them
673 26.8 Advancing the TAPC state
678 26.9 CID allocation
679 26.10 Increasing STL performance with SScan Scan Formats
26.11 An approach to implementing SScan Scan Formats
686 26.12 Where to find examples
687 27. T5 TAP.7
27.1 Introduction
688 27.2 Deployment
689 27.3 Capabilities
27.4 Register and command portfolio
696 27.5 Configurations
698 27.6 Start-up behavior
27.7 Configuration Faults
699 27.8 Enabling transport
700 27.9 Transport Packet composition
701 27.10 Directive Elements
712 27.11 Register Elements
713 27.12 Data Elements
716 27.13 Selection of control and data targets
717 27.14 Data Channel Client functions
719 27.15 Partitioning of the Transport Control Function
722 27.16 Programming considerations
725 28. Transport operation and interfaces
28.1 Introduction
28.2 TAP interface
736 28.3 Transport State Machine
743 28.4 PDCx/DCC interface
750 28.5 Five-bit directives
753 28.6 Eight-bit directives
754 28.7 12-bit directives
757 28.8 DCC interface operation
759 28.9 An approach to implementing the Transport Function
774 29. Test concepts
29.1 Introduction
29.2 Interoperability
775 29.3 Construction of the unit under test
29.4 Background (IEEE 1149.1 paradigm)
777 29.5 Implications for test applications arising from this standard
778 29.6 Test exampleā€”a narrative
779 29.7 Describing the unit under test
780 29.8 Documentation model
781 29.9 Considerations for large-system applications
783 30. Documenting IEEE 1149.7 test endpoints (BSDL.7)
30.1 Introduction
784 30.2 Conventions
30.3 Purpose of BSDL.7
30.4 Scope of BSDL.7
785 30.5 Expectations of a BSDL.7 parser
30.6 Relationship of BSDL.7 to BSDL.1
786 30.7 Lexical elements of BSDL.7
30.8 BSDL.7 reserved words
787 30.9 Components of a BSDL.7 description
30.10 The entity description (BSDL.7)
799 30.11 The Standard VHDL Package STD_1149_7_2009
800 30.12 A typical application of BSDL.7
803 31. Documenting IEEE 1149.7 test modules (HSDL.7)
31.1 Introduction
31.2 Conventions
804 31.3 Purpose of HSDL.7
31.4 Scope of HSDL.7
805 31.5 Expectations of an HSDL.7 parser
31.6 Relationship of HSDL.7 to BSDL.7 (and BSDL.1)
806 31.7 Lexical elements of HSDL.7
31.8 HSDL.7 reserved words
31.9 Components of an HSDL.7 description
807 31.10 The entity description (HSDL.7)
819 31.11 The Standard VHDL Package STD_1149_7_2009_module
31.12 Applications of HSDL.7
827 Annex A (informative) IEEE 1149.1 reference material
830 Annex B (informative) Scan examples in timing diagram form
857 Annex C (informative) Scan examples in tabular form
899 Annex D (informative) Programming considerations
928 Annex E (informative) Recommended electrical characteristics
929 Annex F (informative) Connectivity/electrical recommendations
1014 Annex G (informative) Utilizing SScan Scan Formats
1018 Annex H (informative) The RTCK signal
1026 Annex I (informative) Bibliography
1027 Index
1-C
1028 C
1029 C-D
1030 D-G
1031 G-N
1032 O-P
1033 P-R
1034 R-S
1035 S-T
1036 T
1037 T-Z

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IEEE 1149.7-2009
$208.54