IEEE 1181 1991
$79.08
IEEE Recommended Practice for Latchup Test Methods for CMOS and BiCMOS Integrated- Circuit Process Characterization
| Published By | Publication Date | Number of Pages |
| IEEE | 1991 | 35 |
New IEEE Standard – Inactive – Withdrawn. Withdrawn Standard. Withdrawn Date: Mar 06, 2000. No longer endorsed by the IEEE. Recommendations are provided for the layout and test methods required to characterize properly latchup behavior in CMOS and BiCMOS integrated circuit processes or other processes that have similar lateral PNPN topographical layout characteristics. The aim is to allow the characterization of an integrated circuit process architecture so that different approaches can be scientifically compared. This allows the evaluation of the process capabilities on a worst-case recommended structure and test method independent of an actual integrated circuit product topographical latchup layout practices. Test structures and test philosophy are covered.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 1 | Title Page |
| 3 | Introduction Participants |
| 4 | CONTENTS |
| 5 | 1. General 1.1 Scope 1.2 Purpose |
| 6 | 2. References 3. Definitions and Nomenclature 3.1 Definitions |
| 9 | 3.2 Nomenclature |
| 10 | 4. CMOS Latchup Test Structures 4.1 Introduction 4.2 Unguarded Four-Stripe PNPN |
| 18 | 5. Unguarded Six-Stripe Inverter 5.1 Introduction |
| 21 | 5.2 Output Overvoltage |
| 23 | 5.3 Output Undervoltage 5.4 Substrate Current Triggered Latchup |
| 27 | 6. Test Philosophy 6.1 Test Procedure |
| 29 | 6.2 Hazards |
| 30 | Annex A—Alternate Latchup Test Device — Illustrations |
| 35 | Annex B—CMOS Latchup — Standard Test Procedure — Illustrations |
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