IEEE 1212 1992

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IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses

Published By	Publication Date	Number of Pages
IEEE	1992	138

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Description

New IEEE Standard – Inactive – Superseded. Superseded by IEEE Std 1212-2001 A common bus architecture (which includes functional componentsmodules, nodes, and unitsand their address space, transaction set, CSRs, and configuration information) suitable for both parallel and serial buses is provided in this standard. Bus bridges are enabled by the architecture, but their details are beyond its scope. Configuration information is self-administered by vendors and organizations based upon IEEE Registration Authority company_id.

PDF Catalog

PDF Pages	PDF Title
15	1 Document Structure and Notation 1.1 Document Structure 1.2 References 1.3 Conformance Levels
16	1.4 Technical Glossary
22	Bit Byte and Quadlet Ordering Byte and Quadlet Ordering
23	1.6 Numerical Values C Code Notation CSR ROM and Field Notation C Expression Summary
24	Register Specification Format CSR Addressing Conventions
26	Reserved Registers and Fields Unimplemented Register (hardwired to zero)
27	2 Objectives and Scope 2.1 Scope 2.2 Objectives
29	Transaction Set Requirements 3.1 Transaction Overview Read and Write Transactions Required Transaction Types
30	Noncoherent Lock Transactions Optional Transaction Types
31	Simplified Lock Model
32	3.4 Transaction Errors Subcommand Values for Lock4 and Lock8
33	3.5 Immediate Effects Responder CSR Processing Model
34	CSRs with Special Split-Responder Effects
35	4 Node Addressing 4.1 Node Addresses 4.2 Extended Addressing 32-Bit Extended Addresses
36	32-Bit Extended Addresses
37	64-Bit Fixed Addressing 64-Bit Extended Addresses 64-Bit Extended Addresses
38	4.4 Private Addresses Initial Node Space 64-Bit Fixed Addressing
39	Extended Address Spaces Initial Node Space Components
40	4.7 Indirect Space Configurable Extended Addresses
41	Indirect Space Mapping (address less than 1 Kbytes) Indirect Space Mapping (address greater or equal to 1 Kbytes)
42	Address Space Offsets ROM-Specified Offsets in the Initial Units Space ROM-Specified Offsets in Extended Units Space
44	5 Node Architectures Modules Nodes and Units Simple Single-Bus System
45	5.2 Node States
46	Node States Types of Node Reset
47	5.3 Node Testing 5.3.1 Access-Path Tests 5.3.3 Diagnostic Tests Initialization Test Interface
48	Diagnostic Test Interface Disruptive Test Interface
49	Non-Standard Diagnostic Tests 5.4 Multinode Modules Nondisruptive Test Interface Polled CSR Interrupt Dispatch Model
50	Multinode Module
51	OLR-Defective Module Removal
52	Unit Architecture Overview 6.2.1 Interrupt-Target Registers Synchronized Node Clocks (broadcast backplane model) Synchronized Clocks (pipelined backplane model)
53	6.2.2 Interrupt-Poll Registers Synchronized Clock Registers
54	6.3 Message Passing Globally Synchronized Clocks 6.4.1 Clock Overview
55	6.4.2 Clock Synchronization
56	Clock Update Models
57	Updating Clock Registers
58	Clock Accuracy Requirements Memory Unit Architectures Unit Architecture Environment
60	CSR Definitions Register Names and Offsets CSR Locations
62	CSR Access Modes
63	STATE-CLEAR Format CSRs Access Modes in Nonrunning States
64	7.2 Minimal Implementations Unsupported Register Accesses 7.4 Register Definitions Minimal CSR Register Set
67	Node State Values
68	NODE-IDS Format
70	RESET-START Format
71	7.4.5 INDIRECT-ADDRESS 7.4.6 INDIRECT-DATA INDIRECT-ADDRESS Format
72	7.4.7 SPLIT-TIMEOUT INDIRECT-DATA Format
74	ARGUMENT Register Remote Address Format
75	TEST-START Format cut and tops Formats
76	Special test-step values
77	7.4.10 TEST-STATUS Expected Interpretation of tops Values
78	TEST-STATUS Format test-state Format
79	Test Status Values
80	Test Status Values (successful and unsuccessful phase)
81	7.4.11 UNITS-BASE UNITS-BASE Formats Test Status Values (active phase)
82	7.4.12 UNITS-BOUND UNITS-BOUND Formats
83	Extended Space Alignment and Size
85	7.4.14 MEMORY-BOUND 7.4.15 INTERRUPT-TARGET MEMORY-BOUND Formats
86	7.4.16 INTERRUPT-MASK INTERRUPT-TARGET Format
87	7.4.17 CLOCK-VALUE INTERRUPT-MASK Format CLOCK-VALUE Formats read.only)
88	7.4.18 CLOCK-TICK-PERIOD CLOCK-VALUE Formats (read/write)
89	7.4.19 CLOCK-STROBE-ARRIVED
90	CLOCK-STROBE-ARRIVED Formats (read-only) CLOCK-STROBE-ARRIVED Formats (read/write)
91	7.4.20 CLOCK-STROBE-INFO 7.4.21 Message Targets 7.4.22 ERROR-LOG Registers
93	ROM Specification 8.1 Introduction ROM Design Assumptions 8.1.2 ROM Formats
94	Driver and Diagnostic Identifiers ROM Hierarchy
95	8.1.4 ASCII Text Software Identifier Hierarchy
96	8.1.5 CRC Calculations
97	CRC-16 Update Algorithm CRC-16 Calculation Routine
98	8.2 ROM Formats First ROM Quadlet Minimal ROM Format General ROM Format First ROM Quadlet Minimum ROM Implementation
99	Fully Implemented CSR ROM Directory
100	8.2.4 Directory Formats Directory Structure Directory Entry Format key-type Definitions
101	Immediate Entry Format Offset Entry Format Leaf or Directory Entry Format
102	Calculating Address of Entry Value Fetching ROM From a Desired Offset Address
103	8.2.5 Leaf Format 8.2.6 Textual-Descriptor Leaf Format Textual Descriptor Locations
104	Textual Descriptor Leaf Minimal ASCII Textual Descriptor Leaf Format
105	8.3 bus-info-block Root Directory Entries bus-info-block Format Bus Name Example Values
106	8.4.1 Bus-Dependent-Info 8.4.2 Module-Vendor-Id 8.4.3 Module-Hw-Version 8.4.4 Module-Spec-Id 8.4.5 Module-Sw-Version Root Directory Entries
107	8.4.6 Module-Dependent-Info 8.4.7 Node-Vendor-Id 8.4.8 Node-Hw-Version 8.4.9 Node-Spec-Id 8.4.10 Node-Sw-Version 8.4.11 Node-Capabilities Node Capabilities Entry Format
108	8.4.12 Node-Unique-Id Unique-Id Leaf Format Node Capabilities Bit Field Definitions
109	8.4.1 3 Node-Units-Extent Immediate Value Extent Entry Format Node-Units-Extent CSR Format (offset format) Immediate Value Units Extent Bit Field Definitions
110	8.4.14 Node-Memory-Extent Pointer Value Node-Units-Extent Bit Field Definitions Extended Space Alignment and Size Immediate Memory-Extent Entry-Field Definitions
111	No d e-D e p en den t-I n fo 8.4.16 Unit-Directory Offset Memo ry-Ex ten t En try-Fie1 d Definitions
112	8.5 Unit Directories 8.5.1 Unit-Spec-Id 8.5.2 Unit-Sw-Interface-Id 8.5.3 Unit-Dependent-Info 8.5.4 Unit-Location Unit Directory Entries
113	8.5.5 Unit-Poll-Mask Unit-Locate Leaf Format Unit-Poll Entry Format Unit-Locate.tug Bit Field Definition
114	8.6 Key Definitions key-type and key-value (hexadecimal values)
115	8.7 Company-Ids
116	9 Bus Standard Requirements
117	10 Bibliography
119	A Guide for Using the CSR Architecture A1 Bus Topologies Al.1 Specialized Buses Al.l.l Multiple-Bus Topologies Central Processor/Memory Bus Multiple Bus Configurations
120	Al.1.2 Dual-Port Nodes Serial Bus Extensions Module With Redundant Bus Connections
121	Fault Retry Protocols A1.2 Hardware Fault Recovery Al.2.1 Software Fault Recovery Al.2.2 A2 System Initialization System Initialization Summary A2.1
122	Node Address Assignments A2.2 node-id Address Assignments
123	A2.3 Processor-Cache Model Processor-Cache Model
124	A2.4 Address Protection A2.5 Power Distribution Models TLBs Provide Selective User Protection
125	Power Distribution Model
126	A3 Bus Transactions A3.1 Transaction Overview A3.2 Transaction Components Transaction Components
127	Request Subaction Fields Response Subaction Fields
128	A4 Bus Bridges A4.1 Address-Invariant Mappings CSR Byte Ordering (big-endian)
129	A4.2 Transaction Forwarding Bridge Byte-Line Mapping (big- and little-addressian buses)
130	A4.3 Transaction Ordering Split-Response Transaction Ordering A4.3.1 A4.3.2 Buffered-Write Transparency
131	Nontransparent Request Ordering Nontransparent Response Ordering
132	Weakly Ordered Move Transactions A4.3.3 A4.3.4 Queue-Dependency Deadlocks Bridge Ordering-Shared RequestlResponse FIFOs Deadlock
133	Deadlocked Multiprocessor Interrupts Deadlocked Message Queues
134	A4.4 Address Domains Two Addressing Domains
135	A4.5 Protection Boundaries 32/64-Bit Bridge Mapping-Translations and Conversions
136	A4.6 Coherence Domains Fig A4-10 Remote Subaction Checking
137	Fig A4-11 Limited Coherence Domain

Additional information

Standard Title	IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses
Published Code	IEEE
Publication Date	1992
Pages Count	138

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