IEEE 1364-1995

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IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language

Published By	Publication Date	Number of Pages
IEEE	1995	676

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Description

New IEEE Standard – Superseded. The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.

PDF Catalog

PDF Pages	PDF Title
1	Title Page
3	Introduction
5	Participants
8	CONTENTS
11	1. Overview 1.1 Objectives of this standard 1.2 Conventions used in this standard
12	1.3 Syntactic description
13	1.4 Contents of this standard
14	1.5 Header file listings 1.6 Examples 1.7 Prerequisites
15	2. Lexical conventions 2.1 Lexical tokens 2.2 White space 2.3 Comments 2.4 Operators 2.5 Numbers
19	2.6 Strings
20	2.7 Identifiers, keywords, and system names
23	3. Data types 3.1 Value set 3.2 Nets and registers
25	3.3 Vectors
26	3.4 Strengths 3.5 Implicit declarations 3.6 Net initialization
27	3.7 Net types
32	3.8 Memories
33	3.9 Integers, reals, times, and realtimes
35	3.10 Parameters
36	3.11 Name spaces
37	4. Expressions 4.1 Operators
49	4.2 Operands
52	4.3 Minimum, typical, and maximum delay expressions
53	4.4 Expression bit lengths
55	5. Scheduling semantics 5.1 Execution of a model 5.2 Event simulation
56	5.3 The stratified event queue 5.4 The Verilog simulation reference model
57	5.5 Race conditions
58	5.6 Scheduling implication of assignments
60	6. Assignments 6.1 Continuous assignments
63	6.2 Procedural assignments
65	7. Gate and switch level modeling 7.1 Gate and switch declaration syntax
71	7.2 And, nand, nor, or, xor, and xnor gates
72	7.3 Buf and not gates
73	7.4 Bufif1, bufif0, notif1, and notif0 gates
74	7.5 MOS switches
75	7.6 Bidirectional pass switches
76	7.7 CMOS switches
77	7.8 Pullup and pulldown sources 7.9 Implicit net declarations 7.10 Logic strength modeling
79	7.11 Strengths and values of combined signals
92	7.12 Strength reduction by nonresistive devices 7.13 Strength reduction by resistive devices 7.14 Strengths of net types
93	7.15 Gate and net delays
97	8. User-defined primitives (UDPs) 8.1 UDP definition
100	8.2 Combinational UDPs
101	8.3 Level-sensitive sequential UDPs
102	8.4 Edge-sensitive sequential UDPs
103	8.5 Sequential UDP initialization
105	8.6 UDP instances
106	8.7 Mixing level-sensitive and edge-sensitive descriptions
107	8.8 Level-sensitive dominance
108	9. Behavioral modeling 9.1 Behavioral model overview
109	9.2 Procedural assignments
114	9.3 Procedural continuous assignments
116	9.4 Conditional statement
118	9.5 Case statement
121	9.6 Looping statements
124	9.7 Procedural timing controls
129	9.8 Block statements
133	9.9 Structured procedures
135	10. Tasks and functions 10.1 Distinctions between tasks and functions 10.2 Tasks and task enabling
138	10.3 Functions and function calling
142	11. Disabling of named blocks and tasks
145	12. Hierarchical structures 12.1 Modules
149	12.2 Overriding module parameter value
151	12.3 Ports
156	12.4 Hierarchical names
160	12.5 Scope rules
162	13. Specify blocks 13.1 Specify block declaration
163	13.2 Declaring parameters in specify blocks
164	13.3 Module path declarations
174	13.4 Assigning delays to module paths
177	13.5 Mixing module path delays and distributed delays
178	13.6 Driving wired logic
180	13.7 Controlling pulses on module paths with PATHPULSES
182	14. System tasks and functions
183	14.1 Display system tasks
190	14.2 File input-output system tasks
193	14.3 Timescale system tasks
197	14.4 Simulation control system tasks 14.5 Timing check system tasks
207	14.6 PLA modeling system tasks
210	14.7 Stochastic analysis tasks
212	14.8 Simulation time system functions
214	14.9 Conversion functions for reals
215	14.10 Probabilistic distribution functions
217	15. Value change dump (VCD) file 15.1 Creating the value change dump file
221	15.2 Format of the VCD file
229	16. Compiler directives 16.1 ‘celldefine and ‘endcelldefine 16.2 ‘default_nettype
230	16.3 ‘define and ‘undef
232	16.4 ‘idef, ‘else, ‘endif
234	16.5 ‘include
235	16.6 ‘resetall 16.7 ‘timescale
237	16.8 ‘unconnected_drive and ‘nonunconnected_drive
238	17. PLITF and ACC interface mechanism 17.1 PLI purpose and history
239	17.2 User-defined task or function names 17.3 Overloading built-in system task and function names 17.4 User-supplied PLI applications
240	17.5 Associating PLI applications to a class and system task/function name
241	17.6 PLI application arguments
242	17.7 User-defined system task and function arguments
243	17.8 PLI include files for TF and ACC routines
244	18. Using ACC routines 18.1 ACC routine definition
245	18.2 The handle data type 18.3 Using ACC routines 18.4 List of ACC routines by major category
252	18.5 Accessible objects
259	18.6 ACC routine types and fulltypes
264	18.7 Error handling
266	18.8 Reading and writing delay values
271	18.9 String handling
273	18.10 Using VCL ACC routines
280	19. ACC routine definitions
281	19.1 acc_append_delays()
285	19.2 acc_append_pulsere()
287	19.3 acc_close()
288	19.4 acc_collect()
290	19.5 acc_compare_handles()
291	19.6 acc_configure()
299	19.7 acc_count()
300	19.8 acc_fetch_argc()
301	19.9 acc_fetch_argv()
302	19.10 acc_fetch_attribute()
306	19.11 acc_fetch_attribute_int()
307	19.12 acc_fetch_attribute_str()
308	19.13 acc_fetch_defname()
309	19.14 acc_fetch_delay_mode()
311	19.15 acc_fetch_delays()
315	19.16 acc_fetch_direction()
316	19.17 acc_fetch_edge()
318	19.18 acc_fetch_fullname()
320	19.19 acc_fetch_fulltype()
323	19.20 acc_fetch_index()
325	19.21 acc_fetch_location()
327	19.22 acc_fetch_name()
329	19.23 acc_fetch_paramtype()
330	19.24 acc_fetch_paramval()
332	19.25 acc_fetch_polarity()
333	19.26 acc_fetch_precision()
334	19.27 acc_fetch_pulsere()
337	19.28 acc_fetch_range()
338	19.29 acc_fetch_size()
339	19.30 acc_fetch_tfarg(), acc_fetch_itfarg()
341	19.31 acc_fetch_tfarg_int(), acc_fetch_itfarg_int()
342	19.32 acc_fetch_tfarg_str(), acc_fetch_itfarg_str()
343	19.33 acc_fetch_timescale_info()
345	19.34 acc_fetch_type()
347	19.35 acc_fetch_type_str()
348	19.36 acc_fetch_value()
353	19.37 acc_free()
354	19.38 acc_handle_by_name()
356	19.39 acc_handle_calling_mod_m()
357	19.40 acc_handle_condition()
358	19.41 acc_handle_conn()
359	19.42 acc_handle_datapath()
360	19.43 acc_handle_hiconn()
362	19.44 acc_handle_interactive_scope()
363	19.45 acc_handle_loconn()
364	19.46 acc_handle_modpath()
366	19.47 acc_handle_notifier()
367	19.48 acc_handle_object()
369	19.49 acc_handle_parent()
370	19.50 acc_handle_path()
371	19.51 acc_handle_pathin()
372	19.52 acc_handle_pathout()
373	19.53 acc_handle_port()
375	19.54 acc_handle_scope()
376	19.55 acc_handle_simulated_net()
378	19.56 acc_handle_tchk()
382	19.57 acc_handle_tchkarg1()
384	19.58 acc_handle_tchkarg2()
385	19.59 acc_handle_terminal()
386	19.60 acc_handle_tfarg(), acc_handle_itfarg()
388	19.61 acc_handle_tfinst()
389	19.62 acc_initialize()
390	19.63 acc_next()
394	19.64 acc_next_bit()
396	19.65 acc_next_cell()
397	19.66 acc_next_cell_load()
399	19.67 acc_next_child()
400	19.68 acc_next_driver()
401	19.69 acc_next_hiconn()
403	19.70 acc_next_input()
405	19.71 acc_next_load()
407	19.72 acc_next_loconn()
408	19.73 acc_next_modpath()
409	19.74 acc_next_net()
410	19.75 acc_next_output()
412	19.76 acc_next_parameter()
413	19.77 acc_next_port()
415	19.78 acc_next_portout()
416	19.79 acc_next_primitive()
417	19.80 acc_next_scope()
418	19.81 acc_next_specparam()
419	19.82 acc_next_tchk()
421	19.83 acc_next_terminal()
422	19.84 acc_next_topmod()
423	19.85 acc_object_in_typelist()
425	19.86 acc_object_of_type()
427	19.87 acc_product_type()
429	19.88 acc_product_version()
430	19.89 acc_release_object()
431	19.90 acc_replace_delays()
435	19.91 acc_replace_pulsere()
438	19.92 acc_reset_buffer()
439	19.93 acc_set_interactive_scope()
440	19.94 acc_set_pulsere()
442	19.95 acc_set_scope()
444	19.96 acc_set_value()
450	19.97 acc_vcl_add()
452	19.98 acc_vcl_delete()
453	19.99 acc_version()
454	20. Using TF routines 20.1 TF routine definition 20.2 TF routine parameters 20.3 Reading and writing parameter values
456	20.4 Value change detection 20.5 Simulation time 20.6 Simulation synchronization
457	20.7 Instances of user-defined task or functions 20.8 Module and scope instance names 20.9 Saving information from one system TF call to the next 20.10 Displaying output messages
458	20.11 Stopping and finishing
459	21. TF routine definitions
460	21.1 io_mcdprintf()
461	21.2 io_printf()
462	21.3 mc_scan_plusargs()
463	21.4 tf_add_long()
464	21.5 tf_asynchoff(), tf_iasynchoff()
465	21.6 tf_asynchon(), tf_iasynchon()
466	21.7 tf_clearalldelays(), tf_iclearalldelays()
467	21.8 tf_compare_long()
468	21.9 tf_copypvc_flag(), tf_icopypvc_flag()
469	21.10 tf_divide_long()
470	21.11 tf_dofinish()
471	21.12 tf_dostop()
472	21.13 tf_error()
473	21.14 tf_evaluatep(), tf_ievaluatep()
474	21.15 tf_exprinfo(), tf_iexprinfo()
477	21.16 tf_getcstringp(), tf_igetcstringp()
478	21.17 tf_getinstance()
479	21.18 tf_getlongp(), tf_igetlongp()
480	21.19 tf_getlongtime(), tf_igetlongtime()
481	21.20 tf_getnextlongtime()
482	21.21 tf_getp(), tf_igetp()
483	21.22 tf_getpchange(), tf_igetpchange()
484	21.23 tf_getrealp(), tf_igetrealp()
485	21.24 tf_getrealtime(), tf_igetrealtime()
486	21.25 tf_gettime(), tf_igettime()
487	21.26 tf_gettimeprecision(), tf_igettimeprecision()
488	21.27 tf_gettimeunit(), tf_igettimeunit()
489	21.28 tf_getworkarea(), tf_igetworkarea()
490	21.29 tf_long_to_real()
491	21.30 tf_longtime_tostr()
492	21.31 tf_message()
494	21.32 tf_mipname(), tf_imipname()
495	21.33 tf_movepvc_flag(), tf_imovepvc_flag()
496	21.34 tf_multiply_long()
497	21.35 tf_nodeinfo(), tf_inodeinfo()
501	21.36 tf_nump(), tf_inump()
502	21.37 tf_propagatep(), tf_ipropagatep()
503	21.38 tf_putlongp(), tf_iputlongp()
504	21.39 tf_putp(), tf_iputp()
505	21.40 tf_putrealp(), tf_iputrealp()
506	21.41 tf_read_restart()
507	21.42 tf_real_to_long()
508	21.43 tf_rosynchronize(), tf_irosynchronize()
509	21.44 tf_scale_longdelay()
510	21.45 tf_scale_realdelay()
511	21.46 tf_setdelay(), tf_isetdelay()
512	21.47 tf_setlongdelay(), tf_isetlongdelay()
513	21.48 tf_setrealdelay(), tf_isetrealdelay()
514	21.49 tf_setworkarea(), tf_isetworkarea()
515	21.50 tf_sizep(), tf_isizep()
516	21.51 tf_spname(), tf_ispname()
517	21.52 tf_strdelputp(), tf_istrdelputp()
519	21.53 tf_strgetp(), tf_istrgetp()
520	21.54 tf_strgettime()
521	21.55 tf_strlongdelputp(), tf_istrlongdelputp()
523	21.56 tf_strrealdelputp(), tf_istrrealdelputp()
525	21.57 tf_subtract_long()
527	21.58 tf_synchronize(), tf_isynchronize()
528	21.59 tf_testpvc_flag(), tf_itestpvc_flag()
529	21.60 tf_text()
530	21.61 tf_typep(), tf_itypep()
531	21.62 tf_unscale_longdelay()
532	21.63 tf_unscale_realdelay()
533	21.64 tf_warning()
534	21.65 tf_write_save()
535	22. Using VPI routines 22.1 The VPI interface
536	22.2 Error handling
537	22.3 List ofVPI routines by functional category
540	22.4 Key to object model diagrams
543	22.5 Object data model diagrams
564	23. VPI routine definitions
565	23.1 vpi_chk_error()
566	23.2 vpi_compare_objects()
567	23.3 vpi_free_object()
568	23.4 vpi_get()
569	23.5 vpi_get_cb_info()
570	23.6 vpi_get_delays()
573	23.7 vpi_get_str()
574	23.8 vpi_get_systf_info()
575	23.9 vpi_get_time()
576	23.10 vpi_get_value()
579	23.11 vpi_get_vlog_info()
580	23.12 vpi_handle()
581	23.13 vpi_handle_by_index()
582	23.14 vpi_handle_by_name()
583	23.15 vpi_handle_multi()
584	23.16 vpi_iterate()
585	23.17 vpi_mcd_close()
586	23.18 vpi_mcd_name()
587	23.19 vpi_mcd_open()
588	23.20 vpi_mcd_printf()
589	23.21 vpi_printf()
590	23.22 vpi_put_delays()
592	23.23 vpi_put_value()
594	23.24 vpi_register_cb()
599	23.25 vpi_register_systf()
602	23.26 vpi_remove_cb()
603	23.27 vpi_scan()
604	Annex A—Formal syntax definition
614	Annex B—List of keywords
615	Annex C—The acc_user.h file
625	Annex D—The veriuser.h file
632	Annex E—The vpi_user.h file
645	Annex F—System tasks and functions
652	Annex G—Compiler directives
654	Annex H—Bibliography
655	Index

Additional information

Standard Title	IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language
Published Code	IEEE
Publication Date	1995
Pages Count	676

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IEEE 1364-1995

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