IEEE 1364 1996

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IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language

Published By	Publication Date	Number of Pages
IEEE	1996	676

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Description

New IEEE Standard – Inactive – Superseded. The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.

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PDF Pages	PDF Title
1	Title Page
3	Introduction
5	Participants
8	CONTENTS
11	1. Overview 1.1 Objectives of this standard 1.2 Conventions used in this standard
12	1.3 Syntactic description
13	1.4 Contents of this standard
14	1.5 Header file listings 1.6 Examples 1.7 Prerequisites
15	2. Lexical conventions 2.1 Lexical tokens 2.2 White space 2.3 Comments 2.4 Operators 2.5 Numbers
19	2.6 Strings
20	2.7 Identifiers, keywords, and system names
23	3. Data types 3.1 Value set 3.2 Nets and registers
25	3.3 Vectors
26	3.4 Strengths 3.5 Implicit declarations 3.6 Net initialization
27	3.7 Net types
32	3.8 Memories
33	3.9 Integers, reals, times, and realtimes
35	3.10 Parameters
36	3.11 Name spaces
37	4. Expressions 4.1 Operators
49	4.2 Operands
52	4.3 Minimum, typical, and maximum delay expressions
53	4.4 Expression bit lengths
55	5. Scheduling semantics 5.1 Execution of a model 5.2 Event simulation
56	5.3 The stratified event queue 5.4 The Verilog simulation reference model
57	5.5 Race conditions
58	5.6 Scheduling implication of assignments
60	6. Assignments 6.1 Continuous assignments
63	6.2 Procedural assignments
65	7. Gate and switch level modeling 7.1 Gate and switch declaration syntax
71	7.2 And, nand, nor, or, xor, and xnor gates
72	7.3 Buf and not gates
73	7.4 Bufif1, bufif0, notif1, and notif0 gates
74	7.5 MOS switches
75	7.6 Bidirectional pass switches
76	7.7 CMOS switches
77	7.8 Pullup and pulldown sources 7.9 Implicit net declarations 7.10 Logic strength modeling
79	7.11 Strengths and values of combined signals
92	7.12 Strength reduction by nonresistive devices 7.13 Strength reduction by resistive devices 7.14 Strengths of net types
93	7.15 Gate and net delays
97	8. User-defined primitives (UDPs) 8.1 UDP definition
100	8.2 Combinational UDPs
101	8.3 Level-sensitive sequential UDPs
102	8.4 Edge-sensitive sequential UDPs
103	8.5 Sequential UDP initialization
105	8.6 UDP instances
106	8.7 Mixing level-sensitive and edge-sensitive descriptions
107	8.8 Level-sensitive dominance
108	9. Behavioral modeling 9.1 Behavioral model overview
109	9.2 Procedural assignments
114	9.3 Procedural continuous assignments
116	9.4 Conditional statement
118	9.5 Case statement
121	9.6 Looping statements
124	9.7 Procedural timing controls
129	9.8 Block statements
133	9.9 Structured procedures

Additional information

Standard Title	IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language
Published Code	IEEE
Publication Date	1996
Pages Count	676

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IEEE 1364 1996

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