IEEE 1394 1996

$104.00

IEEE Standard for a High Performance Serial Bus

Published By	Publication Date	Number of Pages
IEEE	1996	392

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Description

New IEEE Standard – Inactive – Superseded. A high-speed serial bus that interates well with most IEEE standard 32-bit and 64-bit parallel buses, as well as such nonbus interconnects as the IEEE Std 1596-1992, Scalable Coherent Interface, is specified. It is intended to provide a low-cost interconnect between cards on the same backplane, cards on other backplanes, and external peripherals. This standard follows the IEEE Std 1212-1991 Command and Status Register (CSR) architecture.

PDF Catalog

PDF Pages	PDF Title
1	Title Page
3	Introduction
4	Participants
7	CONTENTS
9	1. Overview 1.1 Scope 1.2 References
10	1.3 Document organization 1.4 Serial Bus applications
11	1.5 Service model
12	1.6 Document notation
19	1.7 Compliance
20	2. Definitions and abbreviations 2.1 Conformance glossary 2.2 Technical glossary
24	3. Summary description
25	3.1 Node and module architectures 3.2 Topology
27	3.3 Addressing 3.4 Protocol architecture
29	3.5 Transaction layer
32	3.6 Link layer
39	3.7 Physical layer
53	3.8 Bus management
54	4. Cable PHY specification 4.1 Cable PHY services
58	4.2 Cable physical connection specification
89	4.3 Cable PHY facilities
100	4.4 Cable PHY operation
123	5. Backplane PHY specification 5.1 Backplane PHY services
127	5.2 Backplane physical connection specification
136	5.3 Backplane PHY facilities
139	5.4 Backplane PHY operation
146	5.5 Backplane initialization and reset
147	6. Link layer specification 6.1 Link layer services
153	6.2 Link layer facilities
174	6.3 Link layer operation
183	6.4 Link layer reference code
185	7. Transaction layer specification 7.1 Transaction layer services
188	7.2 Transaction facilities
189	7.3 Transaction operation
211	7.4 CSR Architecture transactions mapped to Serial Bus 8. Serial Bus management specification 8.1 Serial Bus management summary
212	8.2 Serial Bus management services
215	8.3 Serial Bus management facilities
242	8.4 Serial Bus management operations
252	8.5 Bus configuration state machines (cable environment)
258	Annex A Cable environment system properties
267	Annex B External connector positive retention
269	Annex C Internal device physical interface
299	Annex D Backplane PHY timing formulas
309	Annex E Cable operation and implementation examples
328	Annex F Backplane physical implementation example
334	Annex G Backplane isochronous resource manager selection
336	Annex H Serial Bus configuration in the cable environment
344	Annex I Socket PCB terminal patterns and mounting
350	Annex J PHY-link interface specification
368	Annex K Serial Bus cable test procedures
387	Annex L Shielding effectiveness and transfer impedance testing