IEEE 1394 2008

$198.79

IEEE Standard for a High-Performance Serial Bus

Published By	Publication Date	Number of Pages
IEEE	2008	954

Guaranteed Safe Checkout

Category: IEEE

If you have any questions, feel free to reach out to our online customer service team by clicking on the bottom right corner. We’re here to assist you 24/7.
Email:[email protected]

Description

Revision Standard – Active. This standard provides specifications for a high-speed serial bus that supports both asynchronous and isochronous communication and integrates well with most IEEE standard 32-bit and 64-bit parallel buses. It is intended to provide a low-cost interconnect between cards on the same backplane, cards on other backplanes, and external peripherals. Interfaces to longer distance transmission media [such as unshielded twisted pair (UTP), optical fiber, and plastic optical fiber (POF)] allow the interconnection to be extended throughout a local network. This standard follows the command and status register (CSR) architecture of IEEE Std 1212-2001.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Standard for a High-Performance Serial Bus
3	Title page
6	Introduction Notice to users Laws and regulations Copyrights Updating of IEEE documents Errata
7	Interpretations Patents Participants
11	Contents
33	List of figures
41	List of tables
49	Importand notice 1. Overview 1.1 Scope and purpose 1.1.1 Scope
50	1.1.2 Purpose 1.2 Document organization 1.3 Serial bus applications 1.3.1 Alternate bus 1.3.2 Low-cost peripheral bus
51	1.3.3 Bus bridge 1.4 Service model
52	1.5 Document notation 1.5.1 Mechanical notation 1.5.2 Signal naming 1.5.3 Size notation
53	1.5.4 Numerical values
54	1.5.5 Packet formats 1.5.6 Register formats 1.5.7 C code notation
56	1.5.8 State machine notation 1.5.9 CSR, ROM, and field notation
57	1.5.10 Register specification format
58	1.5.11 Reserved registers and fields
59	1.5.12 Operation description priorities 1.6 Compliance 1.6.1 CSR architecture compliance
60	1.6.2 Serial bus PHYs
61	2. Normative references
65	3. Definitions, acronyms, and abbreviations 3.1 Definitions
73	3.2 Acronyms and abbreviations
77	4. Short-haul copper connector and cable specification 4.1 Introduction 4.2 6-circuit Alpha connectors and cables
78	4.2.1 6-circuit connectors 4.2.1.1 Connector plug
80	4.2.1.2 Connector plug terminations 4.2.1.3 Connector socket
83	4.2.1.4 Positive retention
84	4.2.1.5 Contact finish on plug and socket contacts
85	4.2.1.6 Termination finish on plug and contact socket terminals 4.2.1.7 Shell finish on plugs and sockets 4.2.1.8 Connector durability 4.2.2 Cables 4.2.2.1 Cable material 4.2.2.2 Cable assemblies 4.2.3 Connector and cable assembly performance criteria
88	4.2.3.1 Performance group A: Basic mechanical dimensional conformance and electrical functionality when subjected to mechanical shock and vibration
89	4.2.3.2 Performance group B: Low-level contact resistance when subjected to thermal shock and humidity stress
90	4.2.3.3 Performance group C: Insulator integrity when subjected to thermal shock and humidity stress
91	4.2.3.4 Performance group D: Contact life and durability when subjected to mechanical cycling and corrosive gas exposure
93	4.2.3.5 Performance group E: Contact resistance and unmating force when subjected to temperature life stress
94	4.2.3.6 Performance group F: Mechanical retention and durability
95	4.2.3.7 Performance group G: General tests
96	4.2.4 Signal propagation performance 4.2.4.1 Signal impedance 4.2.4.2 Signal pairs attenuation
97	4.2.4.3 Signal pairs velocity of propagation 4.2.4.4 Signal pairs relative propagation skew 4.2.4.5 Power pair characteristic impedance 4.2.4.6 Power pair dc resistance
98	4.2.4.7 Crosstalk 4.3 4-circuit Alpha connectors and cables 4.3.1 Connectors 4.3.1.1 Connector plug 4.3.1.2 Connector plug terminations
100	4.3.1.3 Connector socket
102	4.3.1.4 Contact finish on plug and socket contacts 4.3.1.5 Termination finish on plug and contact socket terminals 4.3.1.6 Shell finish on plugs and sockets 4.3.1.7 Connector durability
103	4.3.1.8 PCB footprints
104	4.3.2 Cables 4.3.2.1 Cable material 4.3.2.2 Cable assemblies
105	4.3.3 Connector and cable assembly performance criteria
106	4.3.3.1 Performance group A: Basic mechanical dimensional conformance and electrical functionality when subjected to mechanical shock and vibration
107	4.3.3.2 Performance group B: Low-level contact resistance when subjected to thermal shock and humidity stress
108	4.3.3.3 Performance group C: Insulator integrity when subjected to thermal shock and humidity stress
109	4.3.3.4 Performance group D: Contact life and durability when subjected to mechanical cycling and corrosive gas exposure
111	4.3.3.5 Performance group E: Contact resistance and unmating force when subjected to temperature life stress
112	4.3.3.6 Performance group F: Mechanical retention and durability
113	4.3.3.7 Performance group G: General tests
115	4.3.4 Signal propagation performance criteria 4.3.4.1 Signal impedance 4.3.4.2 Signal pairs attenuation 4.3.4.3 Signal pairs propagation delay
116	4.3.4.4 Signal pairs relative propagation skew 4.3.4.5 Crosstalk 4.4 9-circuit Beta and bilingual connectors and cables 4.4.1 9-circuit Beta and bilingual connectors
118	4.4.1.1 Plug cable termination method 4.4.1.2 Socket
127	4.4.1.3 Mating area finish on plug and socket contacts 4.4.1.4 Termination area finish on plug and socket contacts 4.4.1.5 Shell finish on plugs and sockets 4.4.1.6 Durability
128	4.4.1.7 Socket PCB termination footprints and PHY trace routing
130	4.4.1.8 Plug overmold 4.4.1.9 Socket orientation preference 4.4.2 Cables
131	4.4.2.1 Reference cable material for Beta-to-Beta cable assemblies
132	4.4.2.2 Reference cable material for bilingual-to-Alpha cable assemblies 4.4.2.3 Cable assemblies
136	4.4.3 Connector and cable assembly performance criteria
137	4.4.3.1 Performance group A: Basic mechanical dimensional conformance and electrical functionality when subjected to mechanical shock and vibration
138	4.4.3.2 Performance group B: Low-level contact resistance when subjected to thermal shock and humidity stress
139	4.4.3.3 Performance group C: Insulator integrity when subjected to thermal shock and humidity stress
140	4.4.3.4 Performance group D: Contact life and durability when subjected to mechanical cycling and corrosive gas exposure
142	4.4.3.5 Performance group E: Contact resistance and unmating force when subjected to temperature life stress
143	4.4.3.6 Performance group F: Mechanical retention and durability 4.4.3.7 Performance group G: General tests
145	4.4.4 Signal propagation performance criteria 4.4.4.1 Test hardware 4.4.4.1.1 Connector-only differential test fixture
146	4.4.4.1.2 Cable assembly differential test fixture
147	4.4.4.1.3 Test fixture schematic
148	4.4.4.1.4 Pad position to PHY function map 4.4.4.2 Signal impedance
149	4.4.4.3 Signal pairs attenuation
150	4.4.4.4 Signal pairs velocity of propagation
151	4.4.4.5 Signal pairs intrapair propagation skew
152	4.4.4.6 Crosstalk 4.4.4.6.1 Connector 4.4.4.6.2 Cable assembly 4.4.4.7 Power
153	5. Backplane PHY specification 5.1 Backplane PHY services
154	5.1.1 Backplane PHY bus management services for the management layer 5.1.1.1 PHY control request (PH_CONTROL.request) 5.1.1.2 PHY control confirmation (PH_CONTROL.confirmation)
155	5.1.1.3 PHY event indication (PH_EVENT.indication) 5.1.2 PHY layer arbitration services for the link layer 5.1.2.1 PHY arbitration request (PH_ARB.request)
156	5.1.2.2 PHY arbitration confirmation (PH_ARB.confirmation) 5.1.3 PHY layer data services for the link layer 5.1.3.1 PHY clock indication (PH_CLOCK.indication) 5.1.3.2 PHY data request (PH_DATA.request)
157	5.1.3.3 PHY data indication (PH_DATA.indication) 5.2 Backplane physical connection specification
158	5.2.1 Media attachment 5.2.1.1 Distribution of nodes 5.2.1.2 Fault detection and isolation
159	5.2.1.3 Live insertion 5.2.2 Media signal interface 5.2.2.1 Definition of logic states
160	5.2.2.2 Bit rates 5.2.2.3 Transition times 5.2.2.4 Noise rejection 5.2.3 Media signal timing 5.2.3.1 Backplane transmit data timing
161	5.2.3.2 Backplane receive data timing
162	5.2.3.3 Backplane and transceiver skew 5.2.4 Backplane PHY timing
163	5.2.4.1 Arbitration clock rate 5.2.4.2 Bus synchronization and propagation delay
164	5.2.4.3 Arbitration bit timing
166	5.3 Backplane PHY facilities 5.3.1 Coding 5.3.2 Backplane PHY signals
167	5.3.3 Gap timing
168	5.3.4 Arbitration sequence 5.3.4.1 Arbitration number 5.3.4.2 Priority
169	5.3.4.3 Format of arbitration sequence 5.4 Backplane PHY operation
170	5.4.1 Arbitration 5.4.1.1 Fairness intervals
171	5.4.1.2 Fair arbitration
172	5.4.1.3 Urgent arbitration
173	5.4.1.4 Arbitration by the cycle master 5.4.1.5 Isochronous arbitration 5.4.1.6 Immediate arbitration 5.4.2 Backplane environment packet transmission and reception
174	5.4.2.1 Backplane environment packet transmission
175	5.4.2.2 Backplane environment packet reception
176	5.5 Backplane initialization and reset 5.5.1 Backplane PHY reset 5.5.1.1 Command reset 5.5.1.2 Bus reset 5.5.2 Backplane PHY initialization
177	6. Link layer specification 6.1 Link layer services
178	6.1.1 Link layer bus management services for the node controller 6.1.1.1 Link control request (LK_CONTROL.request)
179	6.1.1.2 Link control confirmation (LK_CONTROL.confirmation) 6.1.1.3 Link event indication (LK_EVENT.indication) 6.1.1.4 Link remote configuration request (LK_CONFIG.request) (cable environment only)
180	6.1.1.5 Link remote configuration indication (LK_CONFIG.indication) (cable environment only) 6.1.2 Link layer asynchronous data services for the transaction layer 6.1.2.1 Link data request (LK_DATA.request)
181	6.1.2.2 Link data confirmation (LK_DATA.confirmation) 6.1.2.3 Link data indication (LK_DATA.indication)
182	6.1.2.4 Link data response (LK_DATA.response) 6.1.2.5 Link bus indication (LK_BUS.indication) 6.1.3 Link layer isochronous data services for application layers 6.1.3.1 Link isochronous control request (LK_ISO_CONTROL.request)
183	6.1.3.2 Link cycle sync indication (LK_CYCLE.indication) 6.1.3.3 Link isochronous request (LK_ISO.request) 6.1.3.4 Link isochronous indication (LK_ISO.indication)
184	6.2 Link layer facilities 6.2.1 Primary packets
185	6.2.2 Asynchronous packets
186	6.2.2.1 Asynchronous packets with no-data payload
187	6.2.2.1.1 Read request for data quadlet 6.2.2.1.2 Write response 6.2.2.2 Asynchronous packet formats with data quadlet payload
188	6.2.2.2.1 Read request for data block 6.2.2.2.2 Write request for data quadlet 6.2.2.2.3 Cycle start
189	6.2.2.2.4 Read response for data quadlet
190	6.2.2.3 Asynchronous packet formats with data block payload 6.2.2.3.1 Write request for data block
191	6.2.2.3.2 Lock request
192	6.2.2.3.3 Read response for data block
193	6.2.2.3.4 Lock response 6.2.3 Isochronous packets 6.2.3.1 Isochronous packet components
194	6.2.3.2 Isochronous data block packet format
195	6.2.4 Asynchronous streams 6.2.4.1 Asynchronous stream packet format
196	6.2.4.2 Global asynchronous stream packet (GASP) format
197	6.2.4.3 Loose vs. strict isochronous packet reception 6.2.5 Primary packet components 6.2.5.1 Reserved fields, codes, and values 6.2.5.2 Destination address 6.2.5.2.1 Destination ID (destination_lD) 6.2.5.2.2 Destination offset (destination_offset)
198	6.2.5.3 Transaction label (tl) 6.2.5.4 Retry code (rt) 6.2.5.5 Transaction code (tcode)
200	6.2.5.6 Priority (pri) 6.2.5.7 Source ID (source_ID) 6.2.5.8 Data length (data_length) 6.2.5.9 Extended transaction code (extended_tcode)
201	6.2.5.10 Response code (rcode) 6.2.5.11 Data field 6.2.5.12 Tag (isochronous stream packets) 6.2.5.13 Channel
202	6.2.5.14 Synchronization code (sy) 6.2.5.15 CRCs 6.2.5.15.1 Definitions
203	6.2.5.15.2 CRC generation equations 6.2.5.15.3 CRC checking 6.2.6 Acknowledge packets
204	6.2.6.1 Acknowledge packet format 6.2.6.2 ACK packet components 6.2.6.2.1 Reserved acknowledge codes 6.2.6.2.2 Acknowledge code (ack_code)
206	6.2.6.2.3 Acknowledge parity (ack_parity) 6.3 Link layer operation 6.3.1 Overview of link layer operation 6.3.1.1 Communication with the PHY layer
207	6.3.1.2 Priority arbitration for PHY packets and response packets 6.3.1.3 Sending an asynchronous packet 6.3.1.4 Receiving an asynchronous packet
208	6.3.1.5 Sending an acknowledge concatenated to an asynchronous packet 6.3.1.6 Isochronous cycles 6.3.1.7 Sending isochronous packets 6.3.1.8 Receiving an isochronous packet
209	6.3.2 Cycle sync event
210	6.3.3 Details of link layer operation
211	6.3.3.1 Link initialization 6.3.3.2 Asynchronous operation
214	6.3.3.3 Isochronous operation
216	6.4 Link layer reference code
219	7. Transaction layer specification 7.1 Transaction layer services 7.1.1 Transaction layer bus management services for SBM
220	7.1.1.1 Transaction control request (TR_CONTROL.request) 7.1.1.2 Transaction control confirmation (TR_CONTROL.confirmation) 7.1.1.3 Transaction event indication (TR_EVENT.indication) 7.1.2 Transaction layer data services for applications and bus management
221	7.1.2.1 Transaction data request (TR_DATA.request) 7.1.2.2 Transaction data confirmation (TR_DATA.confirmation)
222	7.1.2.3 Transaction data indication (TR_DATA.indication) 7.1.2.4 Transaction data response (TR_DATA.response)
223	7.2 Transaction facilities 7.2.1 Split transaction timer 7.2.2 Transaction retry limit 7.3 Transaction operation 7.3.1 Overview of transaction layer operations
224	7.3.1.1 Read transactions 7.3.1.2 Write transactions
225	7.3.1.3 Lock transactions 7.3.1.4 Response codes (rcode) 7.3.1.4.1 No response 7.3.1.4.2 resp_complete
226	7.3.1.4.3 resp_conflict_error 7.3.1.4.4 resp_data_error 7.3.1.4.5 resp_type_error
227	7.3.1.4.6 resp_address_error 7.3.1.5 Error handling 7.3.2 Transaction completion definitions
228	7.3.2.1 Unified transaction 7.3.2.2 Split transaction 7.3.2.3 Concatenated transaction 7.3.2.4 Broadcast transaction 7.3.2.5 Pending transaction 7.3.3 Details of transaction layer operation
229	7.3.3.1 Outbound transaction state machine 7.3.3.1.1 Outbound transaction state machine initialization
230	7.3.3.1.2 Sending a transaction request
231	7.3.3.1.3 Sending a transaction response
232	7.3.3.2 Inbound transaction state machine 7.3.3.2.1 Inbound transaction state machine initialization
233	7.3.3.2.2 Responding to a transaction request
235	7.3.3.2.3 Responding to a transaction response
236	7.3.4 Transaction types 7.3.4.1 Read transactions 7.3.4.2 Write transactions 7.3.4.3 Lock transactions
237	7.3.5 Retry protocols
238	7.3.5.1 Outbound subaction retry protocol
239	7.3.5.2 Inbound subaction single-phase retry protocol 7.3.5.3 Inbound subaction dual-phase retry protocol
242	7.4 CSR architecture transactions mapped to serial bus
245	8. Serial bus management (SBM) specification 8.1 SBM summary 8.1.1 Node control 8.1.2 IRM (cable environment) 8.1.3 IRM (backplane environment) 8.1.4 Bus manager (cable environment)
246	8.2 SBM services 8.2.1 Serial bus control request (SB_CONTROL.request)
247	8.2.2 Serial bus control confirmation (SB_CONTROL.confirmation) 8.2.3 Serial bus event indication (SB_EVENT. indication)
249	8.3 SBM facilities 8.3.1 Node capabilities taxonomy 8.3.1.1 Repeater (cable environment) 8.3.1.2 Transaction capable
250	8.3.1.3 Isochronous capable 8.3.1.4 Cycle master capable 8.3.1.5 IRM capable 8.3.1.6 Bus manager capable (cable environment)
251	8.3.2 Command and status registers 8.3.2.1 Reset conditions
252	8.3.2.2 CSR architecture core registers 8.3.2.2.1 STATE_CLEAR register
254	8.3.2.2.2 STATE_SET register 8.3.2.2.3 NODE_IDS register
255	8.3.2.2.4 Command reset effects 8.3.2.2.5 INDIRECT_ADDRESS and INDIRECT_DATA registers 8.3.2.2.6 SPLIT_TIMEOUT register
256	8.3.2.2.7 ARGUMENT, TEST_START, and TEST_STATUS registers
257	8.3.2.2.8 UNITS_BASE, UNITS_BOUND, MEMORY_BASE, and MEMORY_BOUND registers 8.3.2.2.9 INTERRUPT_TARGET and INTERRUPT_MASK registers 8.3.2.2.10 CLOCK_VALUE, CLOCK_TICK_PERIOD, CLOCK_STROBE_ARRIVED, and CLOCK_INFO registers 8.3.2.2.11 MESSAGE_REQUEST and MESSAGE_RESPONSE registers 8.3.2.3 Serial-Bus-dependent registers
258	8.3.2.3.1 CYCLE_TIME register
259	8.3.2.3.2 BUS_TIME register
260	8.3.2.3.3 POWER_FAIL_IMMINENT register 8.3.2.3.4 POWER_SOURCE register
261	8.3.2.3.5 BUSY_TIMEOUT register
262	8.3.2.3.6 PRIORITY_BUDGET register
263	8.3.2.3.7 BUS_MANAGER_ID register
264	8.3.2.3.8 BANDWIDTH_AVAILABLE register
266	8.3.2.3.9 CHANNELS_AVAILABLE register
267	8.3.2.3.10 MAINT_CONTROL register
268	8.3.2.3.11 MAINT_UTILITY register
269	8.3.2.3.12 BROADCAST_CHANNEL register 8.3.2.4 Unit registers
270	8.3.2.5 TOPOLOGY_MAP registers (cable environment)
271	8.3.2.6 Configuration ROM
272	8.3.2.6.1 Organizationally Unique Identifier (OUI) 8.3.2.6.2 Minimal ROM format 8.3.2.6.3 General ROM format
273	8.3.2.6.4 Configuration ROM Bus_Info_Block
275	8.3.2.6.5 Root_Directory
276	8.3.2.6.6 Unit_Directories
277	8.3.3 SBM variables 8.4 SBM operations 8.4.1 Bus configuration procedures (backplane environment)
278	8.4.1.1 Unmanaged bus (backplane environment) 8.4.1.2 Determination of the IRM (backplane environment) 8.4.1.3 Determination of the cycle master (backplane environment) 8.4.2 Bus configuration procedures (cable environment) 8.4.2.1 Unmanaged bus (cable environment)
279	8.4.2.2 Prior isochronous traffic (cable environment) 8.4.2.3 Determination of the IRM (cable environment)
280	8.4.2.4 Reallocation of prior isochronous resources (cable environment) 8.4.2.5 Determination of the bus manager (cable environment) 8.4.2.6 Determination of the cycle master (cable environment)
281	8.4.2.7 Determination of the root (cable environment)
282	8.4.2.8 Power management by the IRM (cable environment) 8.4.2.9 Allocation of new isochronous resources (cable environment) 8.4.3 Isochronous resource allocation (cable environment) 8.4.3.1 Bandwidth allocation
283	8.4.3.2 Channel allocation
284	8.4.3.3 Bandwidth set-aside 8.4.3.4 Isochronous requests with no cycle master 8.4.4 Power management (cable environment)
285	8.4.4.1 PHY power management 8.4.4.2 Link power management 8.4.4.3 Unit power management 8.4.4.4 Power management by the bus manager
286	8.4.4.5 Power management by the IRM 8.4.5 Topology management (cable environment) 8.4.5.1 Accessing the topology map
287	8.4.5.2 Gap count optimization 8.4.6 Filtered packets on an asynchronous-only B_bus 8.5 Bus configuration state machines (cable environment)
288	8.5.1 Candidate cycle master states
289	8.5.2 Candidate IRM states
290	8.5.3 Candidate bus manager states
292	8.5.4 Abdication by the bus manager
293	9. Short-haul copper PMD electrical specification 9.1 Introduction 9.1.1 Short-haul copper PHY operation
295	9.1.2 Short-haul copper physical connection specification
296	9.1.3 Interfaces 9.1.4 Modes of operation 9.2 Data-strobe (DS) mode specification 9.2.1 Port interface
298	9.2.1.1 Signal amplitude
299	9.2.1.2 Common mode voltage
300	9.2.1.3 Speed signaling
301	9.2.1.4 Arbitration signal voltages
302	9.2.1.5 Input impedance 9.2.1.6 Noise
303	9.2.1.7 Driver and receiver fault protection 9.2.2 Media signal timing 9.2.2.1 Data rate 9.2.2.2 Data signal rise and fall times
304	9.2.2.3 Jitter and skew 9.2.3 Coding 9.2.4 DS PHY signals
305	9.2.5 DS PHY line states
307	9.2.6 Cable PHY timing constants
312	9.2.7 Gap timing
313	9.2.8 Speed signal sampling and filtering
314	9.2.9 Data transmission and reception 9.2.9.1 Data transmission
315	9.2.9.2 Data reception and repeat 9.3 Beta mode specification 9.3.1 Transmitter electrical specifications
319	9.3.2 Receiver electrical specifications
323	9.3.2.1 S3200 equalization 9.3.3 Electrical measurements 9.3.3.1 Transmit rise and fall time 9.3.3.2 Transmit skew
324	9.3.3.3 Transmit eye (normalized and absolute) 9.3.3.4 Rise and fall time setting for receiver jitter tolerance test 9.3.3.5 Skew setting for receiver jitter tolerance test
325	9.3.3.6 Receiver jitter tolerance 9.3.3.7 Minimum amplitude for receiver jitter tolerance test
326	9.3.3.8 S3200 BER 9.3.3.9 S3200 electrical test configuration 9.3.4 DC biasing
327	9.3.5 Toning and signal detect 9.3.5.1 Connection tone
328	9.3.5.2 PMD signal detect function
329	9.3.5.3 Application note 9.3.6 Jitter specifications
333	9.3.7 Intrapair skew 9.3.8 Termination and isolation 9.3.8.1 Bilingual port termination and isolation
334	9.3.8.2 Beta-only port termination and isolation
335	9.3.8.3 PIL-FOP termination and isolation
336	9.4 Cable power and ground 9.4.1 Node power classes
338	9.4.2 Ground isolation
339	9.4.2.1 Primary power providers 9.4.2.2 Secondary power provider 9.4.3 Protection against late VG
343	10. Glass optical fiber (GOF) PMD specification
344	10.1 PMD block diagram 10.2 PMD-to-MDI optical specifications
345	10.3 Transmitter optical specifications 10.4 Receiver optical specifications
346	10.5 Worst-case connection optical power budget and penalties
347	10.6 Optical jitter specifications
349	10.7 Optical measurement requirements 10.7.1 Center wavelength and spectral width measurements 10.7.2 Optical power measurements 10.7.3 Extinction ratio measurements 10.7.4 Relative intensity noise (RIN) 10.7.5 Transmitter optical waveform (transmit eye)
350	10.7.6 Transmit rise and fall characteristics
351	10.7.7 Receiver sensitivity measurements 10.7.8 Jitter measurements 10.8 CPR measurement 10.9 Optical connection cabling model 10.9.1 Characteristics of the fiber optic medium
352	10.9.2 Optical fiber and cable 10.9.3 Multimode connector insertion loss 10.9.4 Optical connection return loss 10.10 Optical connection
353	10.11 Fiber launch conditions: OFL
355	11. PMD specification of fiber media with PN connector 11.1 Scope
356	11.2 PMD block diagram 11.3 Cables
357	11.4 Connector
358	11.5 Connector and cable assembly performance criteria 11.6 Optical fiber interface 11.7 Optical jitter specifications 11.8 Permitted number of segments
363	12. Unshielded twisted pair (UTP) PMD specification
364	12.1 Overview 12.2 PMD block diagram 12.3 Operation of UTP connections
365	12.4 Media specification 12.4.1 100 Ohm UTP connection segment specification 12.4.2 100 Ohm UTP cable specification 12.4.3 Connecting hardware
366	12.4.4 Media interface connector
367	12.4.5 Autocrossover 12.5 PMD electrical specifications 12.5.1 Galvanic isolation
368	12.5.2 Transmitter specifications
371	12.5.3 Receiver specifications 12.5.3.1 Receiver input signals 12.5.3.2 PMD signal detect function
373	12.6 PMD implementation
375	13. Beta mode port specification 13.1 Overview
376	13.2 Port functions 13.2.1 Overview
377	13.2.2 Naming conventions 13.2.3 Control mapping
378	13.2.4 Request types 13.2.4.1 BOSS arbitration request mapping
380	13.2.4.2 Configuration requests 13.2.5 Scrambling
381	13.2.5.1 Data scrambling
382	13.2.5.2 Request symbol scrambling
383	13.2.5.3 Control symbol scrambling
384	13.2.6 Coding 13.2.6.1 8B/10B character coding for data and request types
385	13.2.6.1.1 8B/10B run length and dc balance 13.2.6.1.2 8B/10B code construction 13.2.6.1.3 8B/10B valid data characters
394	13.2.6.1.4 8B/10B valid special characters 13.2.6.2 Control coding
395	13.2.6.2.1 Valid control code characters 13.2.6.2.2 Control code run length and dc balance
396	13.2.6.2.3 Control code error detection 13.2.7 Character transmission 13.2.8 Decoding 13.2.8.1 Bit and character synchronization 13.2.8.2 Data and control character decoding and error detection 13.2.8.3 Special character decoding 13.2.9 Receiver running disparity
397	13.2.10 Descrambling 13.3 Beta mode port operation 13.3.1 Transmit operations 13.3.1.1 Control transmission
398	13.3.1.2 Request transmission 13.3.1.3 Packet transmission
399	13.3.1.4 Speed signaling
400	13.3.1.5 Payload transmission
401	13.3.2 Receive operations 13.3.2.1 Port training 13.3.2.1.1 Loss of synchronization detection procedure 13.3.2.1.2 Resynchronization procedure
402	13.3.2.2 Control reception 13.3.2.3 Request type reception
403	13.3.2.4 DATA_PREFIX reception 13.3.2.5 Speed code determination
404	13.3.2.6 Payload reception
405	13.3.2.7 Error reporting 13.4 Beta port state machines
406	13.4.1 Port transmit state machine
407	13.4.2 Port receive state machine
409	14. Connection management 14.1 Overview
410	14.2 Port characteristics 14.2.1 Requirements
411	14.2.2 Properties 14.3 Functions, variables, and constants
414	14.4 Node-level port controller 14.5 Port connection manager state machine
419	14.6 Standby
420	14.6.1 Nephew node characteristics 14.6.2 Uncle node characteristics
421	14.7 Loop prevention 14.7.1 Test port
422	14.7.2 Loop test data (LTD) 14.7.2.1 M bit 14.7.2.2 G bit
423	14.7.2.3 test_value number 14.7.3 Holding register (HR) 14.7.4 Maximum occupancy timer 14.7.5 Loop test symbol (LTS)
424	14.7.6 Loop test packet (LTP) 14.7.7 Test port selection 14.7.8 Loop test
425	14.7.9 Completing the attach
426	14.7.10 Received ATTACH_REQUEST or bus reset 14.7.11 Loop Disabled state 14.7.12 Connections to Alpha nodes 14.7.13 Loop detection during bus initialization
427	14.7.14 Minimal LTP support 14.7.15 Isolated node behavior 14.8 Connection management 14.8.1 Connection detection 14.8.2 Connection detection and mode determination algorithm
428	14.8.3 Beta-mode speed negotiation
430	14.8.4 Disabled ports
431	14.9 T-mode connectivity and operation 14.10 Simultaneous support for Beta mode and T-mode 14.11 Negotiation 14.11.1 Overview
432	14.11.2 S100 Beta mode parallel negotiation 14.11.2.1 Clause 22 in IEEE Std 802.3-2005 14.11.3 Differences between T-mode and IEEE 802.3 negotiation
433	14.11.3.1 Clause 28 in IEEE Std 802.3-2005 14.11.3.1.1 IEEE 802.3 (Clause 28) interface to MDI 14.11.3.1.2 IEEE 802.3 (28.3) Auto-Negotiation arbitration state machine(s) 14.11.3.1.3 Subclause 28.3.1 in IEEE Std 802.3-2005
434	14.11.3.1.4 Figure 28-16 in IEEE Std 802.3-2005
435	14.11.3.2 Annex 28A in IEEE Std 802.3-2005 14.11.3.3 Annex 28B in IEEE Std 802.3-2005 14.11.3.4 Annex 28C in IEEE Std 802.3-2005 14.11.3.4.1 IEEE 802.3 (28C.6) Message Code 5 ( OUI tag code)
436	14.11.3.4.2 IEEE 802.3 (28C.10) Message Code 8 (1000BASE-T technology message code) 14.11.3.5 Subclause 40.5 in IEEE Std 802.3-2005 14.11.3.5.1 Subclause 40.5.1.1 in IEEE Std 802.3-2005 14.11.3.5.2 IEEE 802.3 (40.5.1.2) next page usage
437	15. PHY register map 15.1 Arbitration compliance levels 15.1.1 Arbitration Compliance Level A 15.1.2 Arbitration Compliance Level B 15.2 PHY register map for the cable environment
442	15.2.1 Port Status page
446	15.2.2 Vendor Identification page
447	15.3 PHY register map for the backplane environment
448	15.4 Integrated link and PHY
449	16. Data routing, arbitration, and control 16.1 Overview
450	16.2 PHY services
451	16.2.1 Cable PHY bus management services for the management layer 16.2.1.1 PHY control request (PH_CONTROL.request) 16.2.1.2 PHY control confirmation (PH_CONTROL.confirmation) 16.2.1.3 PHY event indication (PH_EVENT.indication)
452	16.2.1.4 PHY event response (PH_EVENT.response) 16.2.1.5 PHY link type inquiry indication (PH_LINK_TYPE.indication) and response (PH_LINK_TYPE.response)
453	16.2.2 PHY arbitration services for the link layer 16.2.2.1 PHY arbitration request (PH_ARB.request)
455	16.2.2.2 PHY arbitration confirmation (PH_ARB.conf) 16.2.3 PHY data services for the link layer
456	16.2.3.1 PHY clock indication (PH_CLOCK.indication) 16.2.3.2 PHY data request (PH_DATA.request)
457	16.2.3.3 PHY data indication (PH_DATA.indication) 16.2.4 PHY-link interface block
458	16.2.5 PMD services for the PHY 16.2.5.1 PMD control request (PMD_CONTROL.request) 16.2.5.2 PMD status request (PMD_STATUS.request) and confirmation (PMD_STATUS.confirmation)
459	16.2.5.3 PMD Beta port data indication (PMD_DATA.indication) 16.2.5.4 PMD Beta port transmit data request (PMD_DATA.request) 16.2.5.5 PMD DS port receive signal request (PMD_DSPORT_SIGNAL.request) and confirmation (PMD_DSPORT_SIGNAL.confirmation)
460	16.2.5.6 PMD DS port receive speed request (PMD_DSPORT_RXSPEED.request) and confirmation (PMD_DSPORT_RXSPEED.confirmation) 16.2.5.7 PMD DS port transmit data request (PMD_DSPORT_DATA.request) 16.2.5.8 PMD DS port transmit arbitration state request (PMD_DSPORT_ARB.request) 16.2.5.9 PMD DS port transmit speed request (PMD_DSPORT_TXSPEED.request)
461	16.2.5.10 PMD DS port TpBias request (PMD_DSPORT_TPBIAS.request) 16.2.5.11 PMD cable power status request (PMD_PS.request) and confirmation (PMD_PS.confirmation) 16.2.5.12 PMD cable speed request (PMD_CABLE_SPEED.request) and confirmation (PMD_CABLE_SPEED.confirmation) 16.3 PHY facilities 16.3.1 PHY packet overview 16.3.1.1 PHY packet transmission and reception
462	16.3.1.2 PHY packet identifier bits 16.3.2 Alpha packet formats
463	16.3.2.1 Alpha self-ID packets
465	16.3.2.2 Alpha Link-on packet 16.3.2.3 Alpha PHY configuration packet
466	16.3.2.4 Alpha extended PHY packets 16.3.2.4.1 Alpha ping packet
467	16.3.2.4.2 Alpha remote access packet 16.3.2.4.3 Alpha remote reply packet
468	16.3.2.4.4 Alpha remote command packet
469	16.3.2.4.5 Alpha remote confirmation packet
470	16.3.2.4.6 Alpha resume packet 16.3.3 Beta PHY packet formats 16.3.3.1 Beta self-ID packets
472	16.3.3.2 Beta Remote command packet
473	16.3.3.3 Beta Remote confirmation packet
474	16.3.3.4 Beta PHY configuration packet
475	16.3.3.5 Loop test packet (LTP)
476	16.3.4 Data packet formats 16.3.4.1 Alpha and Beta packet formats 16.3.4.2 General packet format
477	16.3.4.3 Alpha format with speed code
478	16.3.4.4 Alpha format for S100 packets without speed code
479	16.3.4.5 Beta format for all packet speeds 16.3.4.6 Minimum packet spacing 16.3.4.7 Deletable symbols
480	16.3.4.8 Packet transmission examples 16.3.4.8.1 Alpha S100 packet originated on S800 port of node with an Alpha link 16.3.4.8.2 Alpha S100 packet originated on S800 port of node with a Beta link 16.3.4.8.3 Alpha S200 packet originated on S800 port
481	16.3.4.8.4 Beta S800 packet originated on S800 port 16.3.4.8.5 Beta S800 packet originated on S1600 port 16.3.5 Packet forwarding 16.3.5.1 Packets at speeds greater than the port operating speed 16.3.5.2 Packet forwarding: DS port to Beta port 16.3.5.3 Packet forwarding: Beta port to DS port
482	16.4 Cable PHY operation 16.4.1 C code functions and variables
484	16.4.2 Arbitration 16.4.2.1 DS-mode arbitration 16.4.2.2 Beta-mode arbitration
485	16.4.2.2.1 Beta-mode requests
486	16.4.2.2.2 Beta-mode grants
487	16.4.3 Hybrid bus operation 16.4.3.1 Hybrid bus initialization
488	16.4.3.2 Border node functions 16.4.3.2.1 Synchronization of gap events
489	16.4.3.2.2 Protection of Alpha quiet windows
490	16.4.3.2.3 BOSS PHYs unaware of isochronous interval 16.4.3.3 BORDER request mapping 16.4.3.3.1 Alpha to Beta 16.4.3.3.2 Beta to Alpha 16.4.3.4 Discussion of root outside the Beta cloud
491	16.4.4 Isochronous intervals
494	16.4.5 Bus reset state machine
496	16.4.6 Tree identification state machine
498	16.4.7 Self-identification state machine
501	16.4.8 Arbitration state machine
504	16.4.9 Large diameter networks 16.4.9.1 BOSS_RESTART_TIME
505	16.4.9.2 TEST_INTERVAL
507	17. Parallel PHY-link interface 17.1 Introduction
508	17.2 Alpha (A) PHY-link interface specification
511	17.2.1 Initialization and reset
514	17.2.2 Link-on and interrupt indications 17.2.3 Link requests
519	17.2.3.1 LReq rules
522	17.2.3.2 Acceleration control 17.2.4 Status
524	17.2.5 Transmit
526	17.2.6 Cancel
527	17.2.7 Receive 17.2.8 Electrical characteristics (cable environment) 17.2.8.1 DC signal levels and waveforms
529	17.2.8.2 AC timing
531	17.2.8.3 AC timing
532	17.3 Beta (B) and Beta Plus (B Plus) PHY-link interface specification
533	17.3.1 Beta (B) and Beta Plus (B Plus) PHY-link interface characteristics 17.3.2 PHY-link interface signals 17.3.2.1 PHY signals 17.3.2.2 Link signals
534	17.3.2.3 PHY-Link signal descriptions
535	17.3.2.4 Detailed signal descriptions
536	17.3.2.5 Differentiated signals
537	17.3.3 Interface initialization, reset, and disable 17.3.3.1 LPS signal characteristics
538	17.3.3.2 Interface reset
539	17.3.3.3 Interface disable
540	17.3.3.4 Restoration and initialization 17.3.3.5 Initialization completion sequence
541	17.3.4 LinkOn signal characteristics
542	17.3.5 Link requests and notifications
543	17.3.5.1 Link request characteristics 17.3.5.1.1 Asynchronous packet transmit requests
544	17.3.5.1.2 Cycle Start packet transmit requests 17.3.5.1.3 Immediate packet transmit requests
545	17.3.5.1.4 Isochronous packet transmit requests 17.3.5.1.5 Register Access read or write requests
546	17.3.5.1.6 Restore 17.3.5.2 Link notifications 17.3.5.2.1 Cycle start received notification 17.3.5.2.2 Cycle start due notification
547	17.3.5.3 Link request and notification format
550	17.3.6 Interface data transfers 17.3.6.1 Interface phases 17.3.6.2 Packet reception
551	17.3.6.2.1 Packet reception operation 17.3.6.2.2 Packet reception timing
552	17.3.6.2.3 Packet reception description
553	17.3.6.2.4 Interpacket spacing for received packets 17.3.6.3 Packet transmission
554	17.3.6.3.1 Packet transmit operation 17.3.6.3.2 PHY-link packet transmit timing
557	17.3.6.3.3 PHY-link packet transmission description
558	17.3.6.3.4 Transmit grant types
559	17.3.6.3.5 Additional information encoding
560	17.3.7 Format of received and transmitted data
561	17.3.7.1 S100 data
562	17.3.7.2 S200 data 17.3.7.3 S400 data
563	17.3.7.4 S800 data
564	17.3.7.5 S1600 Data 17.3.7.6 S3200 Data 17.3.8 Status transfers and notifications from the PHY
565	17.3.8.1 Bus Status Transfers 17.3.8.1.1 Serial bus reset indications
566	17.3.8.1.2 Bus Status Transfer format 17.3.8.2 PHY Status Transfers
567	17.3.8.2.1 PHY Interrupt indications 17.3.8.2.2 PHY Register Read indications 17.3.8.2.3 Bus Initialization indications 17.3.8.2.4 PHY Status Transfer format
569	17.3.9 Delays affecting interoperability of PHYs and links 17.3.10 Alpha link support
570	17.3.11 Electrical characteristics 17.3.11.1 DC signal levels and waveforms
572	17.3.11.2 AC timing
575	17.4 Isolation barrier 17.4.1 Introduction 17.4.2 Capacitive isolation barrier
578	17.4.3 Alternative isolation barrier
581	18. PIL-FOP serial interface 18.1 Operating model
582	18.2 PIL-FOP connection management 18.2.1 Power-on 18.2.2 PIL-FOP negotiation
583	18.2.3 PIL-FOP restore 18.2.4 Port restore 18.2.5 Loss of synchronization 18.2.6 Loss of power
584	18.2.7 LPS 18.2.8 Serial bus reset 18.3 Serial bus configuration request types not carried over the PIL-FOP interface 18.4 P2P packet protocol
587	19. PHY C code 19.1 Common declarations and functions
606	19.2 Connection management routines 19.2.1 Node-level connection monitor
615	19.2.2 Port connection manager actions and conditions
635	19.3 Port state machine actions
636	19.3.1 DS port
643	19.3.2 Beta port
659	19.3.3 T-mode port
678	19.4 Border arbitration actions and conditions 19.4.1 Border arbitration functions
702	19.4.2 Request processing
712	19.4.3 Bus reset
715	19.4.4 Tree identification
716	19.4.5 Self-identification
721	19.5 Border arbitration
737	20. T-mode port specification 20.1 Overview
738	20.2 Port functions 20.2.1 Port functions overview 20.2.2 Adaptation
739	20.2.2.1 Rate adaptation 20.2.2.2 Clause 40 in IEEE Std 802.3-2005
740	20.2.3 Coding 20.2.3.1 Main properties
741	20.2.4 Symbol types 20.2.5 Data symbols 20.2.6 Arbitration requests
743	20.2.7 Configuration requests 20.2.8 Control symbols in symbol positions A and B 20.2.9 Control symbols in symbol positions C and D
744	20.3 T-mode port operation 20.3.1 Transmit operations 20.3.1.1 Control transmission
745	20.3.1.2 Request transmission 20.3.1.3 Packet transmission 20.3.1.4 Speed signaling 20.3.1.5 Payload transmission
747	20.3.2 Receive operations 20.3.2.1 Symbol decode rules
749	20.3.2.1.1 Loss of synchronization detection procedure
750	20.3.2.2 Control reception 20.3.2.3 Request type reception 20.3.2.4 Speed code determination
751	20.3.2.5 Payload reception 20.3.2.6 Further robustness measures
752	20.3.2.7 Error reporting
753	21. S800 UTP (T-mode) PMD electrical specification
754	21.1 T-mode PMD specification 21.2 T-mode PMD initialization 21.3 Gigabit media independent interface (GMII)
755	21.4 T-mode suspend and resume 21.4.1 Alternative link pulse (ALP) 21.4.2 Suspend 21.4.3 Resume
756	21.5 UTP cable power
757	Annex A (normative) Cable environment electrical isolation A.1 Grounding characteristics of ac-powered devices A.2 Electrical isolation
758	A.3 Agency requirements
761	Annex B (normative) External connector positive retention
763	Annex C (normative) Internal device physical interface C.1 Overview C.2 Electrical interface for internal devices C.2.1 Power requirements
764	C.2.2 Bus signal requirements
765	C.2.3 Miscellaneous signals C.2.4 Signal descriptions
767	C.3 Internal unitized device connectors
769	C.3.1 Internal unitized plug
775	C.3.2 Internal unitized receptacles
779	C.3.3 Connector cable receptacles
782	C.3.4 Cable receptacle termination C.3.5 Cable
783	C.3.6 Contact finish on mating surfaces of plug and receptacle contacts C.3.7 Termination finish on plug and receptacle contact C.3.8 Connector performance criteria
791	Annex D (normative) Backplane PHY timing formulas D.1 Backplane propagation delay
792	D.2 Backplane arbitration timing D.2.1 Synchronization timing
793	D.2.2 Arbitration sample timing D.2.3 Arbitration hold timing
794	D.2.4 Arbitration bit timing D.3 Backplane gap timing
795	D.3.1 Acknowledge gap
796	D.3.2 Subaction gap and arbitration reset gap
797	D.3.3 Arbitration gap scenarios
800	D.4 Backplane environment skew
801	Annex E (normative) Cable operation and implementation examples E.1 Performance optimization
805	E.2 Cable environment jitter budget
807	E.3 Cable PHY configuration example E.3.1 Bus initialization process E.3.2 Tree identify process
811	E.3.3 Self identify process
817	E.3.4 Topology construction
821	Annex F (normative) Backplane physical implementation example F.1 Standardized parallel bus implementations
823	F.2 PHY implementation F.2.1 PHY layer overview
824	F.2.2 High-level PHY logic description
827	Annex G (normative) Backplane IRM selection G.1 Backplane configuration management G.2 IRM selection process G.3 Example of an IRM selection process G.3.1 IRM-capable node environment
828	G.3.2 Non-IRM environment
829	Annex H (normative) Serial bus configuration in the cable environment H.1 Bus configuration timeline
830	H.2 Bus configuration scenarios H.2.1 Bus configuration with a bus manager and an IRM
834	H.2.2 Bus configuration with only an IRM
835	H.3 Combined bus manager and IRM
836	H.4 Abdication by the bus manager
837	Annex I (normative) Socket PCB terminal patterns and mounting I.1 Socket orientation I.2 PCB mounting 0
843	Annex J (normative) Transaction integrity safeguards
845	Annex K (normative) Serial bus cable assembly test procedures K.1 Scope K.2 Test fixtures K.2.1 Cable test fixture
847	K.2.2 Differential test fixture
849	K.3 Signal pairs characteristic and discrete impedance
850	K.3.1 Signal pairs impedance setup calibration-short and load K.3.2 Signal pairs impedance test procedure (connector)
851	K.3.3 Signal pairs impedance limits (connector) K.3.4 IEEE 1394 bulk serial bus cable test methodology
852	K.4 Signal pairs attenuation K.4.1 Signal pairs attenuation setup calibration
853	K.4.2 ATPA
854	K.4.3 ATPB
855	K.4.4 Signal pairs attenuation limits K.4.5 IEEE 1394 bulk serial bus cable test methodology K.5 Signal pairs velocity of propagation
856	K.5.1 Signal pairs velocity of propagation setup calibration K.5.2 VTPA
857	K.5.3 VTPB K.5.4 Signal pairs velocity of propagation limits K.5.5 IEEE 1394 bulk serial bus cable test methodology (TDR)
858	K.5.6 IEEE 1394 bulk serial bus cable test methodology (frequency sweep) K.5.7 Rise and fall time
859	K.5.8 Static shield isolation (insulation resistance) K.6 Signal pairs relative propagation skew
860	K.6.1 Signal pairs skew setup calibration
861	K.6.2 Signal pairs skew test procedure K.6.3 Signal pairs skew limits
862	K.7 Power pair characteristic impedance
863	K.7.1 Power pair impedance setup calibration-short and load K.7.2 Power pair impedance test procedure K.7.3 Power pair dc resistance
864	K.7.4 DC resistance setup calibration
865	K.7.5 DC resistance test procedure K.7.6 DC resistance limits
866	K.8 Crosstalk K.8.1 Crosstalk setup calibration
867	K.8.2 Crosstalk test procedure (between power and signal pairs)
868	K.8.3 Crosstalk test procedure (between signal pairs) K.8.4 Crosstalk limits
869	K.8.5 Crosstalk limits (between signal pairs)
871	Annex L (normative) Shielding effectiveness and transfer impedance testing L.1 Content L.2 Definitions L.3 Test equipment
872	L.4 Theory L.4.1 Reference measurement L.4.2 Sample measurement
873	L.4.3 Calculations L.5 Sample preparation L.5.1 Panel-mounted connector sample
874	L.5.2 Measure sample Zo with TDR L.5.3 Cable-mounted connector sample L.6 Procedure
875	L.7 “Noise floor” plot L.8 Documentation L.8.1 Plots and magnetic files
876	L.8.2 Test report L.9 Performance
877	Annex M (informative) Serial bus topology considerations for power distribution (cable environment)
881	Annex N (normative) Jitter measurements N.1 Test patterns N.2 Random pattern (SB_RPAT) N.3 Receive jitter tolerance pattern (SB_JTPAT)
882	N.4 Supply noise test sequence (SB_SPAT)
883	Annex O (informative) Connection status change
885	Annex P (informative) Deriving bus topology from self-ID packets P.1 Bus topology analysis
886	P.2 Topology analysis after power reset
890	P.3 Topology analysis when the root changes
892	P.4 Topology analysis when a node is inserted
895	Annex Q (informative) Summary description Q.1 Node and module architectures
896	Q.2 Topology Q.2.1 Cable environment
897	Q.2.2 Backplane environment Q.3 Addressing
898	Q.4 Protocol architecture and data transfer services Q.4.1 SBP architecture Q.4.2 Data transfer services
899	Q.5 Transaction layer
900	Q.5.1 Transaction layer services Q.5.2 Lock subcommands
901	Q.5.3 Subaction queue independence
902	Q.6 Link layer
903	Q.6.1 Link layer services
904	Q.6.2 Link and transaction layer interactions
907	Q.6.3 Asynchronous arbitration
908	Q.6.4 Isochronous arbitration
909	Q.7 Physical layer (PHY) Q.7.1 Data bit transmission and reception
910	Q.7.2 Fair arbitration
911	Q.7.3 Cable PHY
919	Q.7.4 Backplane PHY
922	Q.8 Bus management Q.9 New features of IEEE Std 1394a-2000
923	Q.9.1 Connection debounce Q.9.2 Cable arbitration enhancements
927	Q.9.3 Performance optimization via PHY “pinging” Q.9.4 Priority arbitration
928	Q.9.5 Port disable, suspend, and resume
931	Q.10 New features of IEEE Std 1394b-2002 Q.10.1 The relationship to IEEE Std 1394a-2000 Q.10.2 Faster and further
932	Q.10.3 Nomenclature
933	Q.10.4 Media-common properties
934	Q.10.5 Arbitration improvements
940	Q.10.6 PHY-link interface
941	Q.10.7 Miscellaneous features
942	Q.11 New features of IEEE Std 1394c-2006 Q.11.1 Scope
943	Q.11.2 Purpose Q.11.3 T-mode features Q.11.4 The relationship of T-mode to Beta mode Q.11.5 The relationship to IEEE Std 802.3-2005 Q.11.6 S800 over UTP
944	Q.11.7 Twin-mode ports Q.12 New features of IEEE Std 1394-2008 Q.12.1 Errata Q.12.2 Enhanced UTP PMD
945	Q.12.3 Beta PMD electrical specification Q.12.4 Beta Plus PHY-link interface Q.12.5 Bus topology determination Q.12.6 Document organization
947	Annex R (informative) Glossary R.1 Conformance R.2 Definitions
953	Annex S (informative) Bibliography