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IEEE 1450.4 2017:2018 Edition

$62.92

IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for Test Flow Specification

Published By Publication Date Number of Pages
IEEE 2018 190
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New IEEE Standard – Active. This standard extends IEEE Std 1450-1999 (STIL) to 39 provide an interface between test generation tools and test equipment with regard to the specification of the flow of execution of test program components. It defines structures such that test flows, sub-flows, and binning may be described in a manner that facilitates automated generation, modification, and/or manual maintenance, and although not yet a complete run-time test language, execution on automated test equipment (ATE). It defines an interface between tester configurations (described by IEEE Std 1450-1999 and IEEE 1450.2-2002) and test program components. It defines a hierarchy of flows, sub-flows, and test components. It defines structures for defining flow related variables and processing expressions involving those variables. It provides structures that support automatic test program generation (ATPRG) and translation, and running it natively as an ATE programming language. As an adjunct, IEEE Std 1450.3-2007, may be used by ATPRG for tester rules checking.

PDF Catalog

PDF Pages PDF Title
1 IEEE Std 1450.4™-2017 Front Cover
2 Blank Page
3 Title page
5 Important Notices and Disclaimers Concerning IEEE Standards Documents
8 Participants
9 Introduction
10 Contents
13 List of Figures
15 List of Tables
16 Blank Page
17 1. Overview
1.1 General
19 1.2 Scope
1.3 Purpose
2. Normative references
20 3. Definitions, abbreviations, and acronyms
3.1 Definitions
22 3.2 Acronyms and abbreviations
23 4. Preface
4.1 General
4.2 Word usage
4.3 Conventions
24 4.4 Semantics
5. Tutorial
5.1 General
5.2 Flow test program example
27 5.3 FlowExtended test program example
29 6. Extensions to STIL.0 Clause 6 (STIL syntax description)
6.1 General
6.2 Additional reserved words
31 6.3 Additions to STIL.0 Table 3 (SI units)
6.4 Extensions to STIL.0 6.6 (token length)
32 6.5 Extensions to STIL.0 6.8 (user-defined name characteristics)
6.6 Extensions to STIL.0 6.12 (number characteristics)
6.7 Extensions to STIL.0 6.16 (STIL name spaces and name resolution)
33 6.8 Expressions
38 6.9 Functions
40 6.10 Enum
41 6.11 Parameter, MethodParameter, and FlowVariable types
42 7. Extensions to STIL.0 Clause 8 (STIL statement)
7.1 General
44 7.2 STIL syntax
7.3 STIL example
8. Extensions to STIL.0 Clause 14 (Signals block) (FlowExtended)
8.1 General
8.2 Signals block syntax and examples
55 9. Extensions to STIL.0 Clause 15 (SignalGroups block) (FlowExtended)
56 10. Extensions to STIL.0 Clause 16 (PatternExec block) (FlowExtended)
10.1 General
10.2 PatternExec block syntax
11. Extensions to STIL.0 Clause 17 (PatternBurst block) (FlowExtended)
11.1 General
11.2 Extensions to STIL.0 17.1 (PatternBurst block syntax)
57 12. Extensions to STIL.0 Clause 18 (Timing and WaveformTable block) (FlowExtended)
58 12.2 Timing and WaveformTable syntax
13. Extensions to STIL.0 Clause 19 (Spec and Selector blocks)
59 13.2 Spec block syntax
60 14. Extensions to STIL.2 Clause 10 (DCLevels block) (FlowExtended)
14.1 General
14.2 DCLevels block syntax
61 15. Extensions to STIL.2 Clause 12 (DCSequence) (FlowExtended)
15.2 DCSequence block syntax
62 15.3 DCSequence block example
63 16. Include enhancements
16.1 IncludeOnce
16.2 DomainInclude
65 17. FlowVariables
17.1 General
17.2 FlowVariables syntax
67 17.3 FlowVariables examples
69 17.4 FlowVariable access
70 17.5 FlowVariable types
76 17.6 FlowVariable attributes
79 17.7 FlowVariable operators and member functions
81 17.8 FlowVariable array operations
82 18. Device to tester interface
83 19. SignalMap
19.1 General
84 19.2 SignalMap syntax
86 19.3 SignalMap examples
91 20. Device (FlowExtended)
20.1 General
98 20.2 STIL.2: DC levels
20.3 Chip
99 20.4 Package
100 20.5 Channel map
102 20.6 Multi-site/MPW testing
20.7 Device block examples
110 21. Binning
21.1 General
21.2 Binning element reference
111 22. SoftBinDefs
22.1 SoftBinDefs syntax
112 22.2 SoftBinDefs examples
113 22.3 Bins
115 22.4 Bin None (FlowExtended)
116 22.5 Bin axes
22.6 countSince functions (FlowExtended)
117 23. HardBinDefs
23.1 HardBinDefs syntax
118 23.2 HardBinDefs examples
23.3 Bins
119 24. BinMap
24.1 General
24.2 BinMap syntax
120 24.3 BinMap example
25. Flow conceptual model
123 26. Flow conceptual model (FlowExtended)
26.1 General
126 26.2 Flow-related types
26.3 Inheritance
128 26.4 Instantiation and execution
27. TestBase definition (FlowExtended)
27.1 TestBase syntax
132 27.2 TestBase example
133 27.3 Parameter initialization and assignment
134 27.4 Parameter types
139 27.5 Parameter attributes
27.6 Parameter operators and member functions
140 27.7 Parameter array operations
27.8 Spec variable access
142 28. TestType definition (FlowExtended)
28.1 General
28.2 TestType syntax
144 28.3 TestType example
145 29. Test
29.1 General
29.2 Test syntax
147 29.3 Test example
149 30. FlowNode
30.1 General
150 30.2 FlowNode syntax
152 30.3 FlowNode examples
153 31. FlowType definition (FlowExtended)
31.1 FlowType syntax
32. Flow
32.1 General
154 32.2 Flow syntax
155 32.3 Flow examples
156 33. Actions and flow control
158 34. TestProgram
34.1 General
159 34.2 TestProgram syntax
160 34.3 TestProgram examples
161 34.4 Entry points
34.5 Bin map
162 35. Standard definitions
35.1 Standard enumerated types
164 35.2 Standard global variables (FlowExtended)
165 35.3 Flow control defaults (FlowExtended)
170 35.4 Standard No-op and None (FlowExtended)
35.5 Standard PatternExec test (FlowExtended)
171 35.6 Standard functional test (FlowExtended)
172 35.7 Standard flow (FlowExtended)
174 Annex A (informative) Event sequence
A.1 General
A.2 Parsing and loading
A.3 Execution
175 Annex B (informative) Top-level block sequence (FlowExtended)
B.1 General
B.2 Skeleton and dependencies
177 Annex C (informative) Usage examples (FlowExtended)
C.1 Coding examples
188 Annex D (informative) Switching from Flow to FlowExtended
189 Blank Page
190 Back Cover
IEEE 1450.4 2017
$62.92