IEEE 1450.6.2-2014

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IEEE Standard for Memory Modeling in Core Test Language

Published By	Publication Date	Number of Pages
IEEE	2014

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Description

New IEEE Standard – Active. Reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits is required for system-on-chip (SoC) tests. This standard defines language constructs sufficient to represent the context of a memory core and of the integration of that memory core into an SoC. This facilitates the development and reuse of test and repair mechanisms for memories. This standard also defines constructs that represent the test structures internal to the memory core for reuse in the creation of the tests for the logic outside the memory core. Semantic rules are defined for the language to facilitate interoperability between different entities (the memory core provider, the system integrator, and the automation tool developer) involved in the creation of an SoC. The capabilities are an extension of IEEE Std 1450.6(TM)-2005. As a result of this extension, CTL’s limitations of handling memories are addressed.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1450.6.2-2014 Front cover
3	Title page
5	Important notices and disclaimers concerning IEEE standards documents
8	Participants
9	Introduction
10	Contents
11	Important notice 1. Overview 1.1 General
12	1.2 Memory integration flow 1.3 Scope 1.4 Purpose
13	1.5 Limitations of this standard 1.6 Structure of this standard 2. Normative references
14	3. Definitions, acronyms, and abbreviations 3.1 Definitions
16	3.2 Acronyms and abbreviations
17	4. Extensions to IEEE Std 1450.6™-2005 4.1 CTLMode – Internal block—extension of Data Type attributes
20	4.2 Addition to CTLMode Relation block
21	4.3 Port and Target for Purpose statement—extensions to IEEE Std 1450.6™-2005, Clause 16
22	4.4 Compatibility block—extension to IEEE Std 1450.6™-2005, Clause 16
26	4.5 MemoryStructures block—extension to IEEE Std 1450.6™-2005, Clause 6
27	4.6 FileReference block—extension to IEEE Std 1450.6™-2005, Clause 8
28	5. MemoryRepair block 5.1 Syntax
30	5.2 MemoryRepair block syntax description
32	5.3 MemoryRepair Examples
36	6. MemoryPhysicalOrganization block 6.1 Syntax
37	6.2 MemoryPhysicalOrganization block syntax descriptions
39	6.3 MemoryPhysicalOrganization examples
44	7. Memory CTL Orientation and Capabilities Tutorial 7.1 Example of 3-port (2R/1W) memory with repair
55	7.2 Example of Memory with Pipelining and Bit-Line Twisting
59	7.3 Example of Memory with Bank Addressing
64	7.4 Example of Memory with Error Correction Code
68	7.5 Example of memory with embedded comparators