IEEE 1500-2022

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IEEE Standard Testability Method for Embedded Core-based Integrated Circuits

Published By	Publication Date	Number of Pages
IEEE	2022	168

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Description

Revision Standard – Active. A mechanism for the test of core designs within a system on chip (SoC) is defined. This mechanism is a hardware architecture and the core test language (CTL) is leveraged to facilitate communication between core designers and core integrators.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1500™-2022 Front Cover
2	Title page
4	Important Notices and Disclaimers Concerning IEEE Standards Documents
8	Participants
9	Introduction
12	Contents
15	1. Overview 1.1 Background
16	1.2 Scope 1.3 Purpose 1.4 Word usage
17	1.5 Need 1.6 Access protocols 2. Normative references 3. Definitions, acronyms, and abbreviations 3.1 General
18	3.2 Definitions
23	3.3 Acronyms and abbreviations
25	4. Structure of this standard 4.1 Introduction 4.2 Specifications
26	4.3 Descriptions 4.4 Conventions 5. Introduction and motivations for two compliance levels
27	6. Overview of the IEEE 1500 scalable hardware architecture 6.1 Introduction 6.2 Wrapper serial port (WSP)
28	6.3 Wrapper parallel port (WPP) 6.4 Wrapper instruction register (WIR)
29	6.5 Wrapper bypass register (WBY) 6.6 Wrapper boundary register (WBR) 7. Wrapper instructions 7.1 Introduction
30	7.2 Response of the wrapper circuitry to instructions and data registers
32	7.3 Wrapper instruction rules and naming convention
34	7.4 WS_BYPASS instruction
35	7.5 WS_EXTEST instruction
37	7.6 WP_EXTEST instruction
39	7.7 Wx_EXTEST instruction
40	7.8 WS_SAFE instruction
42	7.9 WS_PRELOAD instruction
44	7.10 WP_PRELOAD instruction
45	7.11 WS_CLAMP instruction
47	7.12 WS_INTEST_RING instruction
49	7.13 WS_INTEST_SCAN instruction
51	7.14 Wx_INTEST instruction
53	8. Wrapper serial port (WSP) 8.1 Introduction 8.2 WSP terminals
55	9. Wrapper parallel port (WPP) 9.1 WPP terminals 10. Wrapper instruction register (WIR) 10.1 Introduction
56	10.2 WIR configuration and DR selection
57	10.3 WIR design
60	10.4 WIR operation
62	11. Wrapper bypass register (WBY) 11.1 WBY register configuration and selection
63	11.2 WBY design
64	11.3 WBY operation
65	12. Wrapper boundary register (WBR) 12.1 Introduction
68	12.2 WBR structure and operation
69	12.3 WBR cell structure and operation
70	12.4 WBR operation events
71	12.5 WBR operation modes
73	12.6 Parallel access to the WBR
76	12.7 WBR cell naming
78	12.8 WBR cell examples
81	12.9 IEEE 1500 WBR example
91	13. Wrapper states 13.1 Wrapper Disabled and Wrapper Enabled states
93	14. WSP timing diagrams 14.1 Introduction 14.2 Specifications
94	14.3 Description
100	14.4 Synchronous reset timing
101	14.5 Timing for fast pipelined shift
103	15. WSP configurations for IEEE 1500 system chips 15.1 Introduction 15.2 Connecting multiple WSPs
108	16. Plug-and-play (PnP) 16.1 Introduction 16.2 Background and definition
110	16.3 PnP aspects of standard instructions 16.4 PnP limitations on protocols 16.5 Non-PnP in IEEE Std 1500
111	17. Compliance definitions common to wrapped and unwrapped cores 17.1 Introduction 17.2 General rules
113	17.3 Per terminal rules
115	17.4 Test pattern information rules
118	18. Compliance definitions specific to unwrapped cores 18.1 General rules
119	18.2 Per terminal rules
120	18.3 Additional test information rules 19. Compliance definitions specific to wrapped cores 19.1 General rules
121	19.2 Per terminal rules
122	19.3 Wrapper protocol information rules 20. IEEE 1500 application 20.1 Introduction 20.2 CTL (IEEE 1450.6) overview
124	20.3 IEEE 1500 examples
153	Annex A (informative) Bubble diagram definition
155	Annex B (informative) Wrapper boundary register (WBR) cell examples
163	Annex C (informative) Relationship of IEEE Std 1500 to IEEE Std 1149.1 and IEEE Std 1687 C.1 Introduction C.2 Example of integrating IEEE 1500 cores within an SoC