IEEE 1505.1-2019
$70.42
IEEE Standard for the Common Test Interface Pin Map Configuration for High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505
| Published By | Publication Date | Number of Pages |
| IEEE | 2019 | 158 |
Revision Standard – Active. An extension to the IEEE 1505TM receiver fixture interface (RFI) standard specification is provided in this standard. Particular emphasis is placed on defining within the IEEE 1505 RFI standard a more specific set of performance requirements that employ a common scalable: 1) pin map configuration; 2) specific connector modules; 3) respective contacts; 4) recommended switching implementation; and 5) legacy automatic test equipment (ATE) transitional devices. This is intentionally done to standardize the footprint and assure mechanical and electrical interoperability between past and future automatic test systems (ATS).
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 1 | IEEE Std 1505.1-2019 front cover |
| 2 | Title page |
| 4 | Important Notices and Disclaimers Concerning IEEE Standards Documents |
| 7 | Participants |
| 8 | Introduction |
| 9 | Contents |
| 11 | 1. Overview 1.1 Scope 1.2 Purpose 1.3 Statement of the problem |
| 12 | 2. Normative references 3. Definitions, specification terms, acronyms, and abbreviations 3.1 Definitions 3.2 Specification terms |
| 13 | 3.3 Acronyms and abbreviations |
| 15 | 4. Common test interface requirements 4.1 Introduction |
| 16 | 4.2 Common test interface open-system requirements 4.3 Common test interface cost requirements |
| 17 | 4.4 Vertical integration test support requirements 4.5 Common test interface configuration/interoperability requirements 4.6 Maintainability/end-user support requirements 4.7 Scalable architecture requirements |
| 19 | 4.8 Physical framework requirements |
| 25 | 4.9 Reliability requirements |
| 26 | 4.10 Common test interface connector footprint/parametric requirements |
| 30 | 4.11 Common test interface pin map requirements |
| 31 | Annex A (informative)Common test interface signal definitions for pin map A.1 Analog instruments |
| 33 | A.2 Bus |
| 34 | A.3 Digital A.4 Instrument control A.5 Power loads |
| 35 | A.6 Power supplies A.7 Sense and control, direct current power supply, and loads |
| 36 | A.8 Switch |
| 38 | A.9 System |
| 156 | Annex B (informative)Bibliography |
| 158 | Back cover |
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