IEEE 1581 2011

$44.42

IEEE Standard for Static Component Interconnection Test Protocol and Architecture

Published By	Publication Date	Number of Pages
IEEE	2011	61

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Description

New IEEE Standard – Active. IEEE Std 1581 defines a low-cost method for testing the interconnection of discrete, complex memory integrated circuits (ICs) where additional pins for testing are not available and implementing boundary scan (IEEE Std 1149.1(TM)) is not feasible. This standard describes the implementation rules for the test logic and test mode access/exit methods in compliant ICs. The standard is limited to the behavioral description of the implementation and will not include the technical design for the test logic or test mode control circuitry.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1581-2011 Front Cover
3	Title page
6	Introduction Notice to users Laws and regulations
7	Copyrights Updating of IEEE documents Errata Interpretations Patents
8	Participants
10	Contents
11	Important notice 1. Overview 1.1 Scope 1.2 Purpose
12	1.3 Organization of the standard 1.4 Context
14	1.5 IEEE 1581 defect model, detection, and diagnosis 1.5.1 Categories of defects
15	1.5.2 Defects as addressed by IEEE Std 1581
17	1.6 Objectives 2. Normative references 3. Definitions, acronyms, and abbreviations 3.1 Definitions
20	3.2 Acronyms and abbreviations
21	4. Test architecture 4.1 Overview 4.1.1 Description
23	4.1.2 Test mode versus test function 4.2 Combinational test logic architecture 4.2.1 XOR test method 4.2.2 IAX test method 4.2.3 XOR-2 test method 4.3 Test mode architecture
24	4.3.1 Transparent test mode (TTM) 4.3.2 Test pin (TPN) 5. Classification of device pins 5.1 Specification 5.1.1 Rules
25	5.2 Description
26	6. Test mode behavior 6.1 Specification 6.1.1 Rules 6.2 Description
30	7. Test mode control 7.1 Specification 7.1.1 Rules 7.1.2 Permissions 7.2 Description 7.3 Test pin (TPN) 7.3.1 Specification
31	7.3.2 Description
32	7.3.3 PCB application caution in shared use of the test pin 7.4 Transparent test mode (TTM)
33	7.4.1 Nonfunctional stimulus (NFS) method
34	7.4.2 Clock frequency (CKF) method
36	7.4.3 Designated command codes (DCC) method
37	7.4.4 Analog-level (ANL) method
38	7.4.5 Conditional power-up initiation (CPI) method
40	7.4.6 Default power-up initiation (DPI) method
42	7.4.7 Simultaneous input/output (SIO) method
43	7.5 Test pattern partitioning (TPP) 7.5.1 TTP concept
45	7.5.2 Optional device ID
47	7.5.3 Optional control line continuity
49	7.5.4 Optional built-in self-test (BIST) access
50	7.5.5 Optional public commands
51	7.5.6 Optional private commands 7.5.7 Optional secondary test mode control
52	8. Test logic
53	8.1 Specification 8.1.1 Rules
54	8.1.2 Recommendations 8.1.3 Permissions 8.2 Example implementation 1: XOR test logic
55	8.3 Example implementation 2: IAX test logic
57	8.4 Example implementation 3: XOR-2 test logic
59	9. Conformance and documentation 9.1 Conformance 9.1.1 Specification 9.1.2 Description 9.2 Documentation
60	9.2.1 Specification 9.2.2 Description
61	Annex A (informative) Bibliography