IEEE 1685-2022

$151.13

IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows (Approved Draft)

Published By	Publication Date	Number of Pages
IEEE	2022	750

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Description

Revision Standard – Active. Conformance checks for eXtensible Markup Language (XML) data designed to describe electronic systems are formulated by this standard. The meta-data forms that are standardized include components, systems, bus interfaces and connections, abstractions of those buses, and details of the components including address maps, register and field descriptions, and file set descriptions for use in automating design, verification, documentation, and use flows for electronic systems. A set of XML schemas of the form described by the World Wide Web Consortium (W3C(R)) and a set of semantic consistency rules (SCRs) are included. A generator interface that is portable across tool environments is provided. The specified combination of methodology-independent meta-data and the tool-independent mechanism for accessing that data provides for portability of design data, design methodologies, and environment implementations.

PDF Catalog

PDF Pages	PDF Title
1	Front Cover
2	Title page
4	Important Notices and Disclaimers Concerning IEEE Standards Documents
8	Participants
10	Introduction
11	Contents
20	1. Overview 1.1 Scope 1.2 Purpose
21	1.3 Word usage 1.4 Design environment
22	1.4.1 IP-XACT design environment
23	1.4.2 IP-XACT object descriptions 1.4.3 Object interactions
24	1.4.4 IP-XACT generators
25	1.4.5 IP-XACT design environment interfaces 1.4.6 Tight generator interface 1.4.7 Design intellectual property
26	1.5 IP-XACT–enabled implementations 1.5.1 Design environments
27	1.5.2 Point tools 1.5.3 IPs 1.5.4 Generators 1.6 Conventions used 1.6.1 Visual cues (meta-syntax)
28	1.6.2 Notational conventions 1.6.3 Syntax examples 1.6.4 Graphics used to document the schema 1.6.4.1 Elements and attributes 1.6.4.2 Types 1.6.4.3 Groups
29	1.6.4.4 Namespace 1.6.4.5 Diagrams 1.6.4.5.1 Elements and sequences
30	1.6.4.5.2 Elements and choices
31	1.6.4.5.3 Elements, attributes, groups, and attributeGroups
32	1.6.4.5.4 Wildcards 1.7 Use of color in this standard 1.8 Contents of this standard
34	2. Normative references
35	3. Definitions, acronyms, and abbreviations 3.1 Definitions
40	3.2 Acronyms and abbreviations
41	4. Interoperability use model 4.1 Roles and responsibilities 4.1.1 Component IP provider 4.1.2 SoC design IP provider 4.1.3 SoC design IP consumer
42	4.1.4 Design tool supplier 4.2 IP-XACT IP exchange flows 4.2.1 Component or SoC design IP provider use model
43	4.2.2 Generator provider use model 4.2.3 System design tool provider use model
44	5. Interface definition descriptions 5.1 Definition descriptions 5.2 Bus definition 5.2.1 Schema
45	5.2.2 Description
46	5.3 Abstraction definition 5.3.1 Schema 5.3.2 Description
47	5.4 Ports 5.4.1 Schema 5.4.2 Description
48	5.5 Wire ports 5.5.1 Schema
49	5.5.2 Description
50	5.6 Qualifiers 5.6.1 Schema
51	5.6.2 Description
52	5.7 Wire port group 5.7.1 Schema 5.7.2 Description
53	5.8 Wire port mode (and mirrored mode) constraints 5.8.1 Schema 5.8.2 Description
54	5.9 Transactional ports 5.9.1 Schema 5.9.2 Description
55	5.10 Transactional port group 5.10.1 Schema 5.10.2 Description
56	5.11 Packets 5.11.1 Schema 5.11.2 Description
57	5.11.3 packetField 5.11.3.1 Schema 5.11.3.2 Description 5.12 Extending bus and abstraction definitions 5.12.1 Extending bus definitions
58	5.12.2 Extending abstraction definitions
59	5.12.3 Modifying definitions
61	5.13 Clock and reset handling
62	6. Component descriptions 6.1 Component 6.1.1 Schema 6.1.2 Description
64	6.2 Type definitions 6.2.1 Schema
65	6.2.2 Description
66	6.3 Power domains 6.3.1 Schema 6.3.2 Description
67	6.4 Interfaces 6.4.1 Direct interface modes 6.4.2 Mirrored interface modes
68	6.4.3 Monitor interface modes 6.5 Interface interconnections 6.5.1 Direct connection 6.5.2 Mirrored-non-mirrored connection 6.5.3 Monitor connection
69	6.5.4 Broadcast connections 6.5.5 Interface logical to physical port mapping 6.5.5.1 Mapping rules 6.5.5.2 Physical interconnections 6.6 Complex interface interconnections
70	6.6.1 Channel
71	6.6.2 Bridge
72	6.7 Bus interfaces 6.7.1 busInterface 6.7.1.1 Schema 6.7.1.2 Description
73	6.7.2 Abstraction types 6.7.2.1 Schema
74	6.7.2.2 Description 6.7.3 Port map 6.7.3.1 Schema
75	6.7.3.2 Description
76	6.7.4 Interface modes 6.7.4.1 Schema 6.7.4.2 Description
77	6.7.5 Initiator interface 6.7.5.1 Schema 6.7.5.2 Description
78	6.7.6 Target interface 6.7.6.1 Schema 6.7.6.2 Description
79	6.7.7 Mirrored target interface 6.7.7.1 Schema 6.7.7.2 Description
80	6.8 Indirect interfaces 6.8.1 Schema
81	6.8.2 Description
82	6.9 Component channels 6.9.1 Schema 6.9.2 Description
83	6.10 Modes 6.10.1 Schema 6.10.2 Description
84	6.11 Address spaces
85	6.11.1 addressSpaces 6.11.1.1 Schema 6.11.1.2 Description
86	6.11.2 Segments 6.11.2.1 Schema
87	6.11.2.2 Description 6.11.3 Local memory map 6.11.3.1 Schema 6.11.3.2 Description
88	6.12 Memory maps 6.12.1 memoryMaps 6.12.1.1 Schema
89	6.12.1.2 Description
90	6.12.2 Address block 6.12.2.1 Schema 6.12.2.2 Description
91	6.12.3 Address block definition group 6.12.3.1 Schema 6.12.3.2 Description
92	6.12.4 memoryBlockData group 6.12.4.1 Schema 6.12.4.2 Description
94	6.12.5 Bank 6.12.5.1 Schema 6.12.5.2 Description
95	6.12.6 Banked address block 6.12.6.1 Schema
96	6.12.6.2 Description 6.12.7 Banked bank 6.12.7.1 Schema
97	6.12.7.2 Description
98	6.12.8 Banked subspace 6.12.8.1 Schema 6.12.8.2 Description
99	6.12.9 Subspace map 6.12.9.1 Schema 6.12.9.2 Description
100	6.13 Remapping 6.13.1 Memory remap 6.13.1.1 Schema 6.13.1.2 Description
101	6.14 Registers 6.14.1 Register data 6.14.1.1 Schema 6.14.1.2 Description 6.14.2 Register 6.14.2.1 Schema
102	6.14.2.2 Description
103	6.14.3 Register definition group 6.14.3.1 Schema 6.14.3.2 Description
104	6.14.4 Alternate registers 6.14.4.1 Schema 6.14.4.2 Description
105	6.14.5 Alternate register definition group 6.14.5.1 Schema 6.14.5.2 Description
106	6.14.6 Register file 6.14.6.1 Schema 6.14.6.2 Description
107	6.14.7 Register file definition group 6.14.7.1 Schema 6.14.7.2 Description 6.14.8 Register bit fields 6.14.8.1 Schema
108	6.14.8.2 Description
110	6.14.9 Field data group 6.14.9.1 Schema
111	6.14.9.2 Description
113	6.14.10 Write value constraint 6.14.10.1 Schema 6.14.10.2 Description
114	6.14.11 accessRestriction 6.14.11.1 Schema 6.14.11.2 Description
115	6.14.12 Enumeration values 6.14.12.1 Schema 6.14.12.2 Description
116	6.15 Models 6.15.1 Model 6.15.1.1 Schema 6.15.1.2 Description
118	6.15.2 instantiationsGroup 6.15.2.1 Schema 6.15.2.2 Description
119	6.15.3 componentInstantiation 6.15.3.1 Schema
120	6.15.3.2 Description
121	6.15.4 designInstantiation 6.15.4.1 Schema
122	6.15.5 designConfigurationInstantiation 6.15.5.1 Schema
123	6.15.6 Module parameters 6.15.6.1 Schema 6.15.6.2 Description
124	6.15.6.2.1 Typed, non-typed, and runtime parameters classification
126	6.15.6.2.2 Generic parameters mapping in different languages
127	6.15.7 Component ports 6.15.7.1 Schema
128	6.15.7.2 Description
129	6.15.8 Component wire port Types 6.15.8.1 Schema
130	6.15.8.2 Description
131	6.15.9 domainTypeDefs 6.15.9.1 Schema 6.15.9.2 Description 6.15.10 signalTypeDefs 6.15.10.1 Schema
132	6.15.10.2 Description 6.15.11 Component wireTypeDef 6.15.11.1 Schema 6.15.11.2 Description
133	6.15.11.2.1 Constrained and unconstrained array types
134	6.15.11.2.2 Defaults
135	6.15.12 Component driver 6.15.12.1 Schema 6.15.12.2 Description
136	6.15.13 Component driver/clockDriver 6.15.13.1 Schema
137	6.15.13.2 Description
138	6.15.14 Implementation constraints
139	6.15.15 Component wire port constraints 6.15.15.1 Schema 6.15.15.2 Description
140	6.15.16 Port timing constraints 6.15.16.1 Schema 6.15.16.2 Description
141	6.15.17 Load and drive constraint cell specification 6.15.17.1 Schema 6.15.17.2 Description
142	6.15.18 Other clock drivers 6.15.18.1 Schema
143	6.15.18.2 Description 6.15.19 Component transactional port type 6.15.19.1 Schema
144	6.15.19.2 Description
145	6.15.20 Component transactional protocol/payload definition 6.15.20.1 Schema 6.15.20.2 Description
146	6.15.21 Component transactional port type definition 6.15.21.1 Schema 6.15.21.2 Description
147	6.15.22 Component transactional port service 6.15.22.1 Schema 6.15.22.2 Description
148	6.15.23 Component structured port type 6.15.23.1 Schema 6.15.23.2 Description
149	6.15.24 Subports 6.15.24.1 Schema 6.15.24.2 Description
150	6.15.25 Struct Port Type 6.15.25.1 Schema
151	6.15.25.2 Description 6.15.26 Phantom ports
152	6.16 Component generators 6.16.1 Schema 6.16.2 Description
154	6.17 File sets 6.17.1 fileSets 6.17.1.1 Schema 6.17.1.2 Description
155	6.17.2 file 6.17.2.1 Schema 6.17.2.2 Description
157	6.17.3 buildCommand 6.17.3.1 Schema 6.17.3.2 Description
158	6.17.4 defaultFileBuilder 6.17.4.1 Schema 6.17.4.2 Description
159	6.17.5 function 6.17.5.1 Schema 6.17.5.2 Description
160	6.17.6 sourceFile 6.17.6.1 Schema 6.17.6.2 Description 6.18 Clear box elements
161	6.18.1 Schema 6.18.2 Description
162	6.19 Clear box element reference 6.19.1 Schema 6.19.2 Description
163	6.20 CPUs 6.20.1 Schema 6.20.2 Description
165	6.20.3 executableImage 6.20.3.1 Schema 6.20.3.2 Description
166	6.20.4 languageTools 6.20.4.1 Schema 6.20.4.2 Description
167	6.20.5 fileBuilder 6.20.5.1 Schema 6.20.5.2 Description
168	6.21 Reset types 6.21.1 Schema 6.21.2 Description
169	7. Design descriptions 7.1 Design 7.1.1 Schema 7.1.2 Description
171	7.2 Design component instances 7.2.1 Schema 7.2.2 Description
172	7.3 Design interconnections 7.3.1 interconnection 7.3.1.1 Schema
173	7.3.1.2 Description 7.3.2 monitorInterconnection 7.3.2.1 Schema 7.3.2.2 Description
174	7.4 Active, hierarchical, monitored, and monitor interfaces 7.4.1 Schema
176	7.4.2 Description
177	7.5 Design ad hoc connections 7.5.1 Schema 7.5.2 Description
178	7.5.3 Ad hoc wire and structured connection 7.5.4 Ad hoc transactional connection 7.5.5 Interaction rules between an interface-based connection and ad hoc connections
179	7.6 Port references 7.6.1 Schema 7.6.2 Description
181	8. Abstractor descriptions 8.1 Abstractor 8.1.1 Schema
182	8.1.2 Description
183	8.2 Abstractor interfaces 8.2.1 Schema 8.2.2 Description
184	8.3 Abstractor models 8.3.1 Schema 8.3.2 Description
185	8.4 Abstractor views 8.4.1 Schema 8.4.2 Description
186	8.5 Abstractor ports 8.5.1 Schema 8.5.2 Description
187	8.6 Abstractor wire ports 8.6.1 Schema
188	8.6.2 Description
189	8.7 Abstractor transactional port 8.7.1 Schema
190	8.7.2 Description
191	8.8 Abstractor structured ports 8.8.1 Schema
192	8.8.2 Description
193	8.9 Abstractor generators 8.9.1 Schema
194	8.9.2 Description
195	9. Type definitions descriptions 9.1 Type definitions
196	9.1.1 Schema
197	9.1.2 Description
198	9.2 Field access policy definition 9.2.1 Schema 9.2.2 Description
199	9.3 Enumeration definition 9.3.1 Schema 9.3.2 Description
200	9.4 Field definition 9.4.1 Schema 9.4.2 Description
201	9.5 Register definition 9.5.1 Schema 9.5.2 Description
202	9.6 Register file definition 9.6.1 Schema 9.6.2 Description
203	9.7 Address block definition 9.7.1 Schema 9.7.2 Description
204	9.8 Bank definition 9.8.1 Schema 9.8.2 Description
205	9.8.3 Banked definition bank type 9.8.3.1 Schema 9.8.3.2 Description
206	9.9 Memory map definition 9.9.1 Schema 9.9.2 Description
207	9.9.3 Memory map definition bank 9.9.3.1 Schema 9.9.3.2 Description
208	9.10 Memory remap definition 9.10.1 Schema 9.10.2 Description
209	10. Generator chain descriptions 10.1 generatorChain 10.1.1 Schema
210	10.1.2 Description
211	10.2 generatorChainSelector 10.2.1 Schema 10.2.2 Description
212	10.3 generatorChain component selector 10.3.1 Schema 10.3.2 Description
213	10.4 generatorChain generator 10.4.1 Schema 10.4.2 Description
215	11. Design configuration descriptions 11.1 Design configuration
216	11.2 designConfiguration 11.2.1 Schema 11.2.2 Description
217	11.3 interconnectionConfiguration 11.3.1 Schema 11.3.2 Description
218	11.4 abstractorInstance 11.4.1 Schema 11.4.2 Description
219	11.5 viewConfiguration 11.5.1 Schema 11.5.2 Description
220	12. Catalog descriptions 12.1 catalog 12.1.1 Schema
221	12.1.2 Description
222	12.2 ipxactFile 12.2.1 Schema 12.2.2 Description
223	13. Addressing 13.1 Calculating the bit address of a bit in a memory map or address space
225	13.2 Calculating the bus address at the bus interface 13.3 Calculating the address at the indirect interface
226	13.4 Address modifications of a channel 13.5 Address translation in a bridge
227	14. Data visibility 14.1 Mapped address bits mask 14.2 Address modifications of an interconnection 14.3 Bit steering in a channel
228	14.4 Visibility of bits 14.4.1 Visible address ranges 14.4.2 Bit lanes in memory maps
229	14.4.3 Bit lanes in address spaces 14.4.4 Bit lanes in bus interfaces 14.4.5 Bit lanes in channels 14.4.6 Bit steering in initiators and targets
231	Annex A (informative) Bibliography
232	Annex B (normative) Semantic consistency rules B.1 Semantic consistency rule definitions B.1.1 Compatibility of busDefinitions B.1.2 Interface mode of a bus interface B.1.3 Compatibility of abstractionDefinitions B.1.4 Element referenced by configurableElementValue element B.1.5 Memory mapping
233	B.1.6 Port connection equivalence class B.1.7 Logical and physical ports B.1.8 Addressable bus interface B.1.9 Field connection graph
235	B.2 Rule listings B.2.1 Cross-references and VLNVs
239	B.2.2 Interconnections
241	B.2.3 Channels, bridges, and abstractors
244	B.2.4 Monitor interfaces and monitor interconnections
245	B.2.5 Configurable elements
248	B.2.6 Ports
256	B.2.7 Registers
260	B.2.8 Memory maps
261	B.2.9 Addressing
262	B.2.10 Hierarchy
263	B.2.11 Hierarchy and memory maps B.2.12 Constraints
265	B.2.13 Design configurations
266	B.2.14 Expressions
269	B.2.15 Access handles
270	Annex C (normative) Common elements and concepts C.1 accessHandles C.1.1 simpleAccessHandle C.1.1.1 Schema
271	C.1.1.2 Description C.1.2 slicedAccessHandle C.1.2.1 Schema C.1.2.2 Description
272	C.1.3 portAccessHandle C.1.3.1 Schema C.1.3.2 Description
273	C.1.4 sliceType C.1.4.1 Schema C.1.4.2 Description C.1.5 portSliceType C.1.5.1 Schema C.1.5.2 Description
274	C.2 accessPolicies C.2.1 Schema C.2.2 Description
275	C.3 Access resolution
276	C.4 arrays C.4.1 Configurable arrays with arrayId C.4.1.1 Schema C.4.1.2 Description
277	C.4.2 Configurable arrays without arrayId C.4.2.1 Schema C.4.2.2 Description C.4.3 Memory arrays with stride C.4.3.1 Schema C.4.3.2 Description
278	C.4.4 Field arrays with bit stride C.4.4.1 Schema C.4.4.2 Description
279	C.5 assertions C.5.1 Schema C.5.2 Description
280	C.6 attributes C.6.1 Schema
281	C.6.2 Description
282	C.7 complexBaseExpression
283	C.7.1 complexTiedValueExpression C.7.1.1 Schema C.7.1.2 Description C.7.2 qualifiedExpression C.7.2.1 Schema C.7.2.2 Description
284	C.7.3 realExpression C.7.3.1 Schema C.7.3.2 Description
285	C.7.4 signedLongintExpression C.7.4.1 Schema C.7.4.2 Description
286	C.7.5 stringExpression C.7.5.1 Schema C.7.5.2 Description C.7.6 unresolvedStringExpression C.7.6.1 Schema C.7.6.2 Description
287	C.7.7 unresolvedUnsignedBitExpression C.7.7.1 Schema C.7.7.2 Description C.7.8 unresolvedUnsignedPositiveIntExpression C.7.8.1 Schema C.7.8.2 Description
288	C.7.9 unsignedBitExpression C.7.9.1 Schema C.7.9.2 Description C.7.10 unsignedBitVectorExpression C.7.10.1 Schema C.7.10.2 Description
289	C.7.11 unsignedIntExpression C.7.11.1 Schema C.7.11.2 Description
290	C.7.12 unsignedLongintExpression C.7.12.1 Schema C.7.12.2 Description
291	C.7.13 unsignedPositiveIntExpression C.7.13.1 Schema C.7.13.2 Description
292	C.7.14 unsignedPositiveLongintExpression C.7.14.1 Schema C.7.14.2 Description
293	C.8 choices C.8.1 Schema C.8.1.1 Description
294	C.9 configurableElementValues C.9.1 Schema C.9.2 Description
295	C.10 configurableLibraryRefType C.10.1 Schema C.10.2 Description
296	C.11 documentName group C.11.1 Schema C.11.2 Description
297	C.12 Endianness
298	C.13 fieldReferenceGroup C.13.1 Schema C.13.2 Description
300	C.14 fieldSliceReferenceGroup C.14.1 Schema
301	C.14.2 Description C.15 fileSetRef C.15.1 Schema
302	C.15.2 Description C.16 fileType C.16.1 Schema C.16.2 Description
303	C.17 indices C.17.1 Schema C.17.2 Description
304	C.18 libraryRefType C.18.1 Schema C.18.2 Description
305	C.19 Name groups C.19.1 nameGroup group C.19.1.1 Schema C.19.1.2 Description
306	C.19.2 nameGroupNMTOKEN group C.19.2.1 Schema C.19.2.2 Description
307	C.19.3 nameGroupOptional group C.19.3.1 Schema C.19.3.2 Description
308	C.19.4 nameGroupPort group C.19.4.1 Schema C.19.4.2 Description
309	C.19.5 nameGroupString group C.19.5.1 Schema C.19.5.2 Description C.20 nameValuePairType C.20.1 Schema
310	C.20.2 Description C.21 parameters C.21.1 Schema C.21.2 Description
311	C.22 partSelect C.22.1 Schema C.22.2 Description
312	C.23 pathSegments C.23.1 pathSegment C.23.1.1 Schema C.23.1.2 Description C.23.2 portPathSegment C.23.2.1 Schema C.23.2.2 Description
313	C.24 Power constraints C.24.1 transactionalPowerConstraints C.24.1.1 Schema C.24.1.2 Description C.24.2 wirePowerConstraints C.24.2.1 Schema
314	C.24.2.2 Description C.25 range C.25.1 Schema C.25.2 Description
315	C.26 Vectors C.26.1 vectors C.26.1.1 Schema C.26.2 extendedVectorsType C.26.2.1 Schema
316	C.27 vendorExtensions C.27.1 Schema C.27.2 Description C.28 versionedIdentifier group C.28.1 Schema
317	C.28.2 Description C.28.3 Sorting and comparing version elements C.28.3.1 Comparison rules
318	C.28.3.2 Comparison examples C.28.4 Version control
319	C.29 viewRef C.29.1 Schema C.29.2 Description C.30 xml:id C.31 Component vs. Abstraction Definition Ports
321	Annex D (normative) Types D.1 boolean D.2 float D.3 ID or IDREF D.4 instancePath D.5 integer D.6 libraryRefType D.7 Name
322	D.8 NMTOKEN D.9 NMTOKENS D.10 portName D.11 ipxactURI D.12 string D.13 token
323	Annex E (normative) SystemVerilog expressions E.1 Overview E.2 Data-types E.2.1 bit data type E.2.2 byte data type
324	E.2.3 shortint data type E.2.4 int data type E.2.5 longint data type E.2.6 shortreal data type E.2.7 real data type E.2.8 string data type
325	E.2.9 Signed and unsigned data types E.2.10 Unresolved data types E.3 Assignments E.3.1 Single value assignment E.3.2 Parameter type
326	E.3.3 Parameter signing E.3.4 Vector assignment E.3.5 Array assignment
327	E.3.6 Identifiers E.3.7 Identifier references
328	E.3.7.1 Escaped identifier references E.3.7.2 Keywords
329	E.4 Operators
330	E.5 Functions E.5.1 Integer function E.5.2 Real functions
331	E.5.3 String function E.5.3.1 $sformatf()
333	E.5.4 IP-XACT specific functions E.5.4.1 $ipxact_absdefport_value() E.5.4.2 $ipxact_field_value()
334	E.5.4.3 $ipxact_index_value() E.5.4.4 $ipxact_mode_condition() E.5.4.5 $ipxact_packetfield_value() E.5.4.6 $ipxact_port_value()
335	E.5.5 IP-XACT specific escape sequences E.5.5.1 $ipxact_index_value() E.5.5.2 $ipxact_parameter_value()
336	E.6 Expression language formal syntax (BNF) E.6.1 Declarations: declaration data types E.6.2 Behavioral statements: Case statements E.6.2.1 Patterns E.6.2.2 Covergroup declarations
337	E.6.3 Expressions E.6.3.1 Concatenations E.6.3.2 Subroutine calls E.6.3.3 Expressions
338	E.6.3.4 Primaries E.6.3.5 Operators E.6.3.6 Numbers E.6.3.7 Strings E.6.4 General: Identifiers
339	E.7 SystemVerilog conversion steps E.7.1 Convert parameter E.7.2 Convert expression E.8 SystemVerilog reference
342	Annex F (normative) Tight generator interface F.1 Method of communication F.2 Generator invocation
343	F.2.1 Resolving the URL F.2.2 Example
344	F.3 TGI API
345	F.3.1 TGI fault codes F.3.2 Administrative commands
346	F.3.3 Return values F.4 IDs and configurable values
347	F.5 TGI messages F.6 Vendor attributes F.7 TGI calls F.7.1 Category index
349	F.7.2 Abstraction definition (BASE)
355	F.7.3 Abstraction definition (EXTENDED)
366	F.7.4 Abstractor (BASE)
367	F.7.5 Abstractor (EXTENDED)
371	F.7.6 Access Policy (BASE) F.7.7 Access handle (BASE)
372	F.7.8 Access handle (EXTENDED)
373	F.7.9 Access policy (BASE)
380	F.7.10 Access policy (EXTENDED)
387	F.7.11 Address space (BASE)
390	F.7.12 Address space (EXTENDED)
393	F.7.13 Array (BASE)
394	F.7.14 Array (EXTENDED)
396	F.7.15 Assertion (BASE) F.7.16 Assertion (EXTENDED)
397	F.7.17 Bus definition (BASE)
398	F.7.18 Bus definition (EXTENDED)
400	F.7.19 Bus interface (BASE)
407	F.7.20 Bus interface (EXTENDED)
414	F.7.21 CPU (BASE)
416	F.7.22 CPU (EXTENDED)
418	F.7.23 Catalog (BASE)
419	F.7.24 Catalog (EXTENDED)
422	F.7.25 Choice (BASE)
423	F.7.26 Choice (EXTENDED) F.7.27 Clearbox (BASE)
424	F.7.28 Clearbox (EXTENDED)
425	F.7.29 Component (BASE)
428	F.7.30 Component (EXTENDED)
437	F.7.31 Configurable element (BASE)
438	F.7.32 Configurable element (EXTENDED)
439	F.7.33 Constraint (BASE)
442	F.7.34 Constraint (EXTENDED)
444	F.7.35 Constraint Set (BASE)
445	F.7.36 Constraint Set (EXTENDED) F.7.37 Design (BASE)
449	F.7.38 Design (EXTENDED)
455	F.7.39 Design configuration (BASE)
458	F.7.40 Design configuration (EXTENDED)
462	F.7.41 Driver (BASE)
468	F.7.42 Driver (EXTENDED)
471	F.7.43 Element attribute (BASE)
486	F.7.44 Element attribute (EXTENDED)
509	F.7.45 File builder (BASE)
515	F.7.46 File builder (EXTENDED)
521	F.7.47 File set (BASE)
526	F.7.48 File set (EXTENDED)
532	F.7.49 Generator (BASE)
534	F.7.50 Generator (EXTENDED)
536	F.7.51 Generator chain (BASE)
538	F.7.52 Generator chain (EXTENDED)
540	F.7.53 Indirect interface (BASE)
546	F.7.54 Indirect interface (EXTENDED)
552	F.7.55 Instantiation (BASE)
556	F.7.56 Instantiation (EXTENDED)
560	F.7.57 Memory map (BASE)
570	F.7.58 Memory map (EXTENDED)
581	F.7.59 Miscellaneous (BASE)
584	F.7.60 Miscellaneous (EXTENDED)
586	F.7.61 Module parameter (BASE)
587	F.7.62 Module parameter (EXTENDED) F.7.63 Name group (BASE)
588	F.7.64 Name group (EXTENDED)
589	F.7.65 Parameter (BASE)
590	F.7.66 Parameter (EXTENDED)
591	F.7.67 Port (BASE)
605	F.7.68 Port (EXTENDED)
627	F.7.69 Port map (BASE)
629	F.7.70 Port map (EXTENDED)
631	F.7.71 Power (BASE)
632	F.7.72 Power (EXTENDED)
634	F.7.73 Register (BASE)
645	F.7.74 Register (EXTENDED)
655	F.7.75 Register file (BASE)
657	F.7.76 Register file (EXTENDED)
659	F.7.77 Slice (BASE)
664	F.7.78 Slice (EXTENDED)
668	F.7.79 Top element (BASE)
669	F.7.80 Top element (EXTENDED)
671	F.7.81 Type definitions (BASE)
678	F.7.82 Type definitions (EXTENDED)
687	F.7.83 Vector (BASE) F.7.84 Vector (EXTENDED)
688	F.7.85 Vendor extensions (BASE) F.7.86 Vendor extensions (EXTENDED) F.7.87 View (BASE)
690	F.7.88 View (EXTENDED)
691	F.7.89 All ID types
694	Annex G (informative) External bus with an internal/digital interface G.1 Example: Ethernet interfaces
695	G.2 Example: I2C bus
696	Annex H (informative) Bridges and channels
697	H.1 Transparent bridge
698	H.2 Opaque bridge H.2.1 Without an address space segment reference
699	H.2.2 With an address space segment reference
700	H.2.3 Effect of an initiator interface address space base address
702	H.3 Channel with address remapping
703	H.4 Channel with bit steering
706	Annex I (informative) Examples I.1 abstractionDefinition – RTL
708	I.2 abstractionDefinition – TLM
709	I.3 abstractor
710	I.4 busDefinition
711	I.5 catalog
713	I.6 component
737	I.7 design
740	I.8 designConfiguration
741	I.9 fieldAccessPolicyDefinitions
744	I.10 generatorChain
745	I.11 typeDefinitions

Additional information

Standard Title	IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows (Approved Draft)
Published Code	IEEE
Publication Date	2022
Pages Count	750

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IEEE 1685-2022

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