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IEEE 1800.2 2017

$148.42

IEEE Standard for Universal Verification Methodology Language Reference Manual

Published By Publication Date Number of Pages
IEEE 2017 472
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New IEEE Standard – Active. The Universal Verification Methodology (UVM) that can improve interoperability, reduce the cost of using intellectual property (IP) for new projects or electronic design automation (EDA) tools, and make it easier to reuse verification components is provided. Overall, using this standard will lower verification costs and improve design quality throughout the industry. The primary audiences for this standard are the implementors of the UVM base class library, the implementors of tools supporting the UVM base class library, and the users of the UVM base class library. (The PDF of this standard is available at no cost compliments of the GET IEEE program https://ieeexplore.ieee.org/browse/standards/get-program/page)

PDF Catalog

PDF Pages PDF Title
1 IEEE Std 1800.2™-2017 Front cover
2 Title page
4 Important Notices and Disclaimers Concerning IEEE Standards Documents
7 Participants
8 Introduction
10 Contents
14 1. Overview
1.1 Scope
1.2 Purpose
1.3 Conventions used
1.3.1 Visual cues (meta-syntax)
15 1.3.2 Return values
1.3.3 Inheritance
1.3.4 Operation order on equivalent data objects
1.3.5 uvm_pkg
16 1.3.6 Random stability
17 2. Normative references
3. Definitions, acronyms, and abbreviations
3.1 Definitions
18 3.2 Acronyms and abbreviations
19 4. UVM class reference
21 5. Base classes
5.1 Overview
5.2 uvm_void
5.3 uvm_object
5.3.1 Class declaration
5.3.2 Common methods
22 5.3.3 Seeding
5.3.4 Identification
24 5.3.5 Creation
5.3.6 Printing
25 5.3.7 Recording
5.3.8 Copying
26 5.3.9 Comparing
27 5.3.10 Packing
28 5.3.11 Unpacking
29 5.3.12 Configuration
5.3.13 Field operations
32 5.3.14 Active policy
5.4 uvm_transaction
33 5.4.1 Class declaration
5.4.2 Methods
37 5.5 uvm_port_base #(IF)
5.5.1 Class declaration
38 5.5.2 Methods
41 5.6 uvm_time
5.6.1 Class declaration
5.6.2 Common methods
44 6. Reporting classes
6.1 Overview
6.2 uvm_report_message
6.2.1 Class declaration
6.2.2 Common methods
45 6.2.3 Infrastructure references
6.2.4 Message fields
47 6.3 uvm_report_object
48 6.3.1 Class declaration
6.3.2 Common methods
6.3.3 Reporting
50 6.3.4 Verbosity configuration
51 6.3.5 Action configuration
52 6.3.6 File configuration
6.3.7 Override configuration
53 6.3.8 Report handler configuration
6.4 uvm_report_handler
6.4.1 Class declaration
6.4.2 Common methods
54 6.4.3 Verbosity configuration
6.4.4 Action configuration
55 6.4.5 File configuration
56 6.4.6 Override configuration
6.4.7 Message processing
6.5 Report server
6.5.1 uvm_report_server
60 6.5.2 uvm_default_report_server
6.6 uvm_report_catcher
6.6.1 Class declaration
6.6.2 Common methods
61 6.6.3 Current message state
62 6.6.4 Change message state
63 6.6.5 Callback interface
6.6.6 Reporting
66 7. Recording classes
7.1 uvm_tr_database
7.1.1 Class declaration
7.1.2 Common methods
7.1.3 Database API
67 7.1.4 Stream API
7.1.5 Link API
68 7.1.6 Implementation agnostic API
7.2 uvm_tr_stream
7.2.1 Class declaration
7.2.2 Common methods
69 7.2.3 Introspection API
7.2.4 Stream API
70 7.2.5 Transaction recorder API
71 7.2.6 Handles
7.2.7 Implementation agnostic API
72 7.3 UVM links
7.3.1 uvm_link_base
74 7.3.2 uvm_parent_child_link
75 7.3.3 uvm_cause_effect_link
76 7.3.4 uvm_related_link
77 8. Factory classes
8.1 Overview
8.2 Factory component and object wrappers
8.2.1 Introduction
8.2.2 type_id
78 8.2.3 uvm_component_registry #(T,Tname)
79 8.2.4 uvm_object_registry #(T,Tname)
81 8.2.5 Abstract registries
83 8.3 UVM factory
8.3.1 uvm_factory
88 8.3.2 uvm_object_wrapper
89 8.3.3 uvm_default_factory
90 9. Phasing
9.1 Overview
9.2 Implementation
9.2.1 Class hierarchy
9.2.2 Phasing related classes
9.2.3 Common and run-time phases
9.3 Phasing definition classes
9.3.1 uvm_phase
98 9.3.2 uvm_phase_state_change
99 9.3.3 uvm_phase_cb
9.4 uvm_domain
100 9.4.1 Class declaration
9.4.2 Methods
9.5 uvm_bottomup_phase
9.5.1 Class declaration
101 9.5.2 Methods
9.6 uvm_task_phase
102 9.6.1 Class declaration
9.6.2 Methods
9.7 uvm_topdown_phase
9.7.1 Class declaration
103 9.7.2 Methods
9.8 Predefined phases
104 9.8.1 Common phases
105 9.8.2 UVM run-time phases
108 10. Synchronization classes
10.1 Event classes
10.1.1 uvm_event_base
110 10.1.2 uvm_event#(T)
111 10.2 uvm_event_callback
10.2.1 Class declaration
10.2.2 Methods
112 10.3 uvm_barrier
10.3.1 Class declaration
10.3.2 Methods
114 10.4 Pool classes
10.4.1 uvm_event_pool
115 10.4.2 uvm_barrier_pool
10.5 Objection mechanism
10.5.1 uvm_objection
119 10.5.2 uvm_objection_callback
120 10.6 uvm_heartbeat
121 10.6.1 Class declaration
10.6.2 Methods
122 10.7 Callbacks classes
10.7.1 uvm_callback
123 10.7.2 uvm_callbacks #(T,CB)
127 11. Container classes
11.1 Overview
11.2 uvm_pool #(KEY,T)
11.2.1 Class declaration
11.2.2 Methods
129 11.3 uvm_queue #(T)
11.3.1 Class declaration
11.3.2 Methods
132 12. UVM TLM interfaces
12.1 Overview
12.2 UVM TLM 1
12.2.1 General
133 12.2.2 Unidirectional interfaces and ports
12.2.3 Bidirectional interfaces and ports
134 12.2.4 uvm_tlm_if_base #(T1,T2)
137 12.2.5 Port classes
138 12.2.6 Export classes
140 12.2.7 Implementation (imp) classes
142 12.2.8 FIFO classes
145 12.2.9 Channel classes
148 12.2.10 Analysis ports
149 12.3 UVM TLM 2
12.3.1 General
12.3.2 uvm_tlm_if: transport interfaces
151 12.3.3 Enumerations
12.3.4 Generic payload and extensions
162 12.3.5 Sockets
165 12.3.6 Port classes
166 12.3.7 Export classes
167 12.3.8 Implementation (imp) classes imps
168 12.3.9 uvm_tlm_time
169 13. Predefined component classes
13.1 uvm_component
13.1.1 Class declaration
13.1.2 Common methods
170 13.1.3 Hierarchy interface
171 13.1.4 Phasing interface
177 13.1.5 Configuration interface
178 13.1.6 Recording interface
182 13.1.7 Other interfaces
13.2 uvm_test
13.2.1 Class declaration
13.2.2 Methods
183 13.3 uvm_env
13.3.1 Class declaration
13.3.2 Methods
13.4 uvm_agent
13.4.1 Class declaration
13.4.2 Methods
184 13.5 uvm_monitor
13.5.1 Class declaration
13.5.2 Methods
13.6 uvm_scoreboard
13.6.1 Class declaration
13.6.2 Methods
185 13.7 uvm_driver #(REQ,RSP)
13.7.1 Class declaration
13.7.2 Ports
13.7.3 Methods
13.8 uvm_push_driver #(REQ,RSP)
186 13.8.1 Class declaration
13.8.2 Ports
13.8.3 Methods
13.9 uvm_subscriber
13.9.1 Class declaration
13.9.2 Ports
13.9.3 Methods
188 14. Sequences classes
14.1 uvm_sequence_item
14.1.1 Class declaration
14.1.2 Common fields
190 14.1.3 Reporting interface
192 14.2 uvm_sequence_base
14.2.1 Class declaration
14.2.2 Common methods
193 14.2.3 Sequence execution
194 14.2.4 Run-time phasing
195 14.2.5 Sequence control
198 14.2.6 Sequence item execution
200 14.2.7 Response API
201 14.3 uvm_sequence #(REQ,RSP)
14.3.1 Class declaration
14.3.2 Variables
202 14.3.3 Methods
14.4 uvm_sequence_library
203 14.4.1 Class declaration
14.4.2 Example
14.4.3 Common methods
14.4.4 Sequence selection
205 14.4.5 Sequence registration
207 15. Sequencer classes
15.1 Overview
15.1.1 Sequencer variants
15.1.2 Sequence item ports
15.2 Sequencer interface
15.2.1 uvm_sqr_if_base #(T1,T2)
211 15.2.2 Sequence item pull ports
212 15.3 uvm_sequencer_base
15.3.1 Class declaration
15.3.2 Methods
216 15.3.3 Requests
217 15.3.4 Responses
15.3.5 Default sequence
218 15.4 Common sequencer API
15.4.1 Method
15.4.2 Request
219 15.4.3 Responses
15.5 uvm_sequencer #(REQ,RSP)
15.5.1 Class declaration
15.5.2 Methods
220 15.6 uvm_push_sequencer #(REQ,RSP)
15.6.1 Class declaration
15.6.2 Ports
15.6.3 Methods
221 16. Policy classes
16.1 uvm_policy
16.1.1 Class declaration
16.1.2 Methods
222 16.1.3 Active object
223 16.1.4 recursion_state_e
16.2 uvm_printer
224 16.2.1 Class declaration
16.2.2 Methods
16.2.3 Methods for printer usage
228 16.2.4 Methods for printer subtyping
229 16.2.5 Methods for printer configuration
232 16.2.6 Methods for object print control
16.2.7 Element stack
233 16.2.8 uvm_printer_element
234 16.2.9 uvm_printer_element_proxy
235 16.2.10 uvm_table_printer
236 16.2.11 uvm_tree_printer
237 16.2.12 uvm_line_printer
238 16.3 uvm_comparer
16.3.1 Class declaration
239 16.3.2 Methods
16.3.3 Methods for comparer usage
242 16.3.4 Methods for comparer configuration
243 16.3.5 Methods for comparer reporting control
16.3.6 Methods for object compare control
244 16.4 uvm_recorder
16.4.1 Class declaration
16.4.2 Methods for recorder configuration
245 16.4.3 Introspection API
16.4.4 Transaction recorder API
246 16.4.5 Handles
247 16.4.6 Attribute recording
249 16.4.7 Implementation agnostic API
252 16.5 uvm_packer
16.5.1 Class declaration
16.5.2 Methods
253 16.5.3 Methods for packer subtyping
254 16.5.4 Packing and unpacking
258 16.6 uvm_copier
16.6.1 Class declaration
16.6.2 Methods
259 16.6.3 Methods for object copy control
16.6.4 Methods for copier usage
261 17. Register layer
17.1 Overview
17.2 Global declarations
17.2.1 Types
262 17.2.2 Enumerations
265 18. Register model
18.1 uvm_reg_block
18.1.1 Class declaration
18.1.2 Methods
267 18.1.3 Introspection
271 18.1.4 Coverage
273 18.1.5 Access
274 18.1.6 Back door
277 18.2 uvm_reg_map
18.2.1 Class declaration
18.2.2 Common methods
18.2.3 Methods
280 18.2.4 Introspection
283 18.2.5 Bus access
285 18.3 uvm_reg_file
18.3.1 Class declaration
18.3.2 Methods
18.3.3 Introspection
286 18.3.4 Back door
287 18.4 uvm_reg
18.4.1 Class declaration
18.4.2 Methods
288 18.4.3 Introspection
291 18.4.4 Access
297 18.4.5 Front door
298 18.4.6 Back door
300 18.4.7 Coverage
303 18.4.8 Callbacks
304 18.5 uvm_reg_field
18.5.1 Class declaration
18.5.2 Common methods
18.5.3 Methods
305 18.5.4 Introspection
308 18.5.5 Access
314 18.5.6 Callbacks
315 18.6 uvm_mem
18.6.1 Class declaration
18.6.2 Variables
18.6.3 Methods
316 18.6.4 Introspection
320 18.6.5 HDL access
323 18.6.6 Front door
18.6.7 Back door
326 18.6.8 Coverage
328 18.6.9 Callbacks
329 18.7 uvm_reg_indirect_data
18.7.1 Class declaration
18.7.2 Methods
330 18.8 uvm_reg_fifo
18.8.1 Class declaration
18.8.2 Common variables
18.8.3 Methods
18.8.4 Introspection
331 18.8.5 Access
333 18.9 uvm_vreg
18.9.1 Class declaration
341 18.9.2 uvm_vreg_cbs
343 18.10 uvm_vreg_field
18.10.1 Class declaration
18.10.2 Methods
18.10.3 Introspection
344 18.10.4 HDL access
345 18.10.5 Callbacks
347 18.10.6 uvm_vreg_field_cbs
348 18.11 uvm_reg_cbs
18.11.1 Class declaration
18.11.2 Methods
352 18.11.3 Types
18.11.4 uvm_reg_read_only_cbs
18.11.5 uvm_reg_write_only_cbs
353 18.12 uvm_mem_mam
18.12.1 Class declaration
18.12.2 Types
354 18.12.3 Variables
18.12.4 Methods
355 18.12.5 Memory management
356 18.12.6 Introspection
18.12.7 uvm_mem_region
359 18.12.8 uvm_mem_mam_policy
360 18.12.9 uvm_mem_mam_cfg
362 19. Register layer interaction with RTL design
19.1 Generic register operation descriptors
19.1.1 uvm_reg_item
365 19.1.2 uvm_reg_bus_op
366 19.2 Classes for adapting between register and bus operations
19.2.1 uvm_reg_adapter
367 19.2.2 uvm_reg_tlm_adapter
368 19.3 uvm_reg_predictor
19.3.1 Class declaration
19.3.2 Variables
369 19.3.3 Methods
370 19.4 Register sequence classes
19.4.1 uvm_reg_sequence
376 19.4.2 uvm_reg_frontdoor
377 19.5 uvm_reg_backdoor
19.5.1 Class declaration
19.5.2 Methods
380 19.6 UVM HDL back-door access support routines
19.6.1 Variables
19.6.2 Methods
382 Annex A (informative) Bibliography
383 Annex B (normative) Macros and defines
408 Annex C (normative) Configuration and resource classes
C.1 Overview
C.2 Resources
417 C.3 UVM resource database
420 C.4 UVM configuration database
423 Annex D (normative) Convenience classes, interface, and methods
D.1 uvm_callback_iter
424 D.2 Component interfaces
428 D.3 uvm_reg_block access methods
430 D.4 Callback typedefs
432 Annex E (normative) Test sequences
E.1 uvm_reg_hw_reset_seq
433 E.2 Bit bashing test sequences
434 E.3 Register access test sequences
436 E.4 Shared register and memory access test sequences
439 E.5 Memory access test sequences
440 E.6 Memory walking-ones test sequences
442 E.7 uvm_reg_mem_hdl_paths_seq
443 E.8 uvm_reg_mem_built_in_seq
444 Annex F (normative) Package scope functionality
F.1 Overview
F.2 Types and enumerations
451 F.3 Methods and types
454 F.4 Core service
459 F.5 Traversal
462 F.6 uvm_run_test_callback
463 F.7 uvm_root
467 Annex G (normative) Command line arguments
G.1 Command line processing
469 G.2 Built-in UVM-aware command line arguments
472 Back cover
IEEE 1800.2 2017
$148.42