IEEE 1800-2012

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IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language

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IEEE	2012	1315

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Description

Revision Standard – Superseded. The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing test benches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit GETIEEE program located at https://ieeexplore.ieee.org/browse/standards/get-program/page for details.)

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1800-2012 Front cover
3	Title page
6	Notice to users Laws and regulations Copyrights Updating of IEEE documents Errata Patents
8	Participants
11	Introduction
13	Contents
28	List of figures
31	List of tables
35	List of syntax excerpts
41	Part One: Design and Verification Constructs
42	Important notice 1. Overview 1.1 Scope 1.2 Purpose 1.3 Content summary
43	1.4 Special terms 1.5 Conventions used in this standard
44	1.6 Syntactic description
45	1.7 Use of color in this standard 1.8 Contents of this standard
48	1.9 Deprecated clauses 1.10 Examples 1.11 Prerequisites
49	2. Normative references
51	3. Design and verification building blocks 3.1 General 3.2 Design elements 3.3 Modules
52	3.4 Programs
53	3.5 Interfaces
54	3.6 Checkers 3.7 Primitives 3.8 Subroutines 3.9 Packages
55	3.10 Configurations 3.11 Overview of hierarchy
56	3.12 Compilation and elaboration
58	3.13 Name spaces
59	3.14 Simulation time units and precision
63	4. Scheduling semantics 4.1 General 4.2 Execution of a hardware model and its verification environment 4.3 Event simulation
64	4.4 Stratified event scheduler
69	4.5 SystemVerilog simulation reference algorithm 4.6 Determinism
70	4.7 Nondeterminism 4.8 Race conditions 4.9 Scheduling implication of assignments
72	4.10 PLI callback control points
73	5. Lexical conventions 5.1 General 5.2 Lexical tokens 5.3 White space 5.4 Comments 5.5 Operators
74	5.6 Identifiers, keywords, and system names
75	5.7 Numbers
80	5.8 Time literals 5.9 String literals
82	5.10 Structure literals
83	5.11 Array literals 5.12 Attributes
85	5.13 Built-in methods
87	6. Data types 6.1 General 6.2 Data types and data objects 6.3 Value set
88	6.4 Singular and aggregate types
89	6.5 Nets and variables
90	6.6 Net types
101	6.7 Net declarations
104	6.8 Variable declarations
106	6.9 Vector declarations
107	6.10 Implicit declarations
108	6.11 Integer data types
109	6.12 Real, shortreal, and realtime data types 6.13 Void data type 6.14 Chandle data type
110	6.15 Class 6.16 String data type
115	6.17 Event data type
116	6.18 User-defined types
117	6.19 Enumerations
123	6.20 Constants
130	6.21 Scope and lifetime
132	6.22 Type compatibility
135	6.23 Type operator
136	6.24 Casting
141	6.25 Parameterized data types
143	7. Aggregate data types 7.1 General 7.2 Structures
145	7.3 Unions
149	7.4 Packed and unpacked arrays
153	7.5 Dynamic arrays
156	7.6 Array assignments
157	7.7 Arrays as arguments to subroutines
158	7.8 Associative arrays
161	7.9 Associative array methods
164	7.10 Queues
169	7.11 Array querying functions 7.12 Array manipulation methods
174	8. Classes 8.1 General 8.2 Overview
175	8.3 Syntax
176	8.4 Objects (class instance)
177	8.5 Object properties and object parameter data
178	8.6 Object methods 8.7 Constructors
180	8.8 Typed constructor calls
181	8.9 Static class properties 8.10 Static methods 8.11 This
182	8.12 Assignment, renaming, and copying
184	8.13 Inheritance and subclasses 8.14 Overridden members
185	8.15 Super
186	8.16 Casting 8.17 Chaining constructors
187	8.18 Data hiding and encapsulation 8.19 Constant class properties
188	8.20 Virtual methods
190	8.21 Abstract classes and pure virtual methods 8.22 Polymorphism: dynamic method lookup
191	8.23 Class scope resolution operator ::
193	8.24 Out-of-block declarations
194	8.25 Parameterized classes
197	8.26 Interface classes
207	8.27 Typedef class 8.28 Classes and structures
208	8.29 Memory management
209	9. Processes 9.1 General 9.2 Structured procedures
213	9.3 Block statements
219	9.4 Procedural timing controls
229	9.5 Process execution threads 9.6 Process control
233	9.7 Fine-grain process control
236	10. Assignment statements 10.1 General 10.2 Overview
237	10.3 Continuous assignments
240	10.4 Procedural assignments
245	10.5 Variable declaration assignment (variable initialization) 10.6 Procedural continuous assignments
247	10.7 Assignment extension and truncation
248	10.8 Assignment-like contexts
249	10.9 Assignment patterns
253	10.10 Unpacked array concatenation
256	10.11 Net aliasing
258	11. Operators and expressions 11.1 General 11.2 Overview
259	11.3 Operators
263	11.4 Operator descriptions
283	11.5 Operands
287	11.6 Expression bit lengths
289	11.7 Signed expressions
290	11.8 Expression evaluation rules
291	11.9 Tagged union expressions and member access
293	11.10 String literal expressions
294	11.11 Operator overloading
296	11.12 Minimum, typical, and maximum delay expressions
298	11.13 Let construct
304	12. Procedural programming statements 12.1 General 12.2 Overview 12.3 Syntax
305	12.4 Conditional if–else statement
310	12.5 Case statement
315	12.6 Pattern matching conditional statements
319	12.7 Loop statements
323	12.8 Jump statements
325	13. Tasks and functions (subroutines) 13.1 General 13.2 Overview 13.3 Tasks
329	13.4 Functions
335	13.5 Subroutine calls and argument passing
340	13.6 Import and export functions 13.7 Task and function names 13.8 Parameterized tasks and functions
342	14. Clocking blocks 14.1 General 14.2 Overview 14.3 Clocking block declaration
344	14.4 Input and output skews
345	14.5 Hierarchical expressions
346	14.6 Signals in multiple clocking blocks 14.7 Clocking block scope and lifetime 14.8 Multiple clocking blocks example
347	14.9 Interfaces and clocking blocks
348	14.10 Clocking block events 14.11 Cycle delay: ##
349	14.12 Default clocking
350	14.13 Input sampling
351	14.14 Global clocking
355	14.15 Synchronous events 14.16 Synchronous drives
360	15. Interprocess synchronization and communication 15.1 General 15.2 Overview 15.3 Semaphores
362	15.4 Mailboxes
365	15.5 Named events
370	16. Assertions 16.1 General 16.2 Overview 16.3 Immediate assertions
373	16.4 Deferred assertions
380	16.5 Concurrent assertions overview
383	16.6 Boolean expressions
384	16.7 Sequences
388	16.8 Declaring sequences
396	16.9 Sequence operations
418	16.10 Local variables
424	16.11 Calling subroutines on match of a sequence
425	16.12 Declaring properties
451	16.13 Multiclock support
461	16.14 Concurrent assertions
478	16.15 Disable iff resolution
480	16.16 Clock resolution
485	16.17 Expect statement
486	16.18 Clocking blocks and concurrent assertions
488	17. Checkers 17.1 Overview 17.2 Checker declaration
491	17.3 Checker instantiation
494	17.4 Context inference
495	17.5 Checker procedures
497	17.6 Covergroups in checkers
498	17.7 Checker variables
504	17.8 Functions in checkers 17.9 Complex checker example
507	18. Constrained random value generation 18.1 General 18.2 Overview 18.3 Concepts and usage
510	18.4 Random variables
512	18.5 Constraint blocks
532	18.6 Randomization methods
533	18.7 In-line constraints—randomize() with
536	18.8 Disabling random variables with rand_mode()
537	18.9 Controlling constraints with constraint_mode()
538	18.10 Dynamic constraint modification
539	18.11 In-line random variable control
540	18.12 Randomization of scope variables—std::randomize()
541	18.13 Random number system functions and methods
543	18.14 Random stability
545	18.15 Manually seeding randomize
546	18.16 Random weighted case—randcase
547	18.17 Random sequence generation—randsequence
557	19. Functional coverage 19.1 General 19.2 Overview
558	19.3 Defining the coverage model: covergroup
560	19.4 Using covergroup in classes
562	19.5 Defining coverage points
573	19.6 Defining cross coverage
582	19.7 Specifying coverage options
587	19.8 Predefined coverage methods
589	19.9 Predefined coverage system tasks and system functions 19.10 Organization of option and type_option members
590	19.11 Coverage computation
595	20. Utility system tasks and system functions 20.1 General
596	20.2 Simulation control system tasks 20.3 Simulation time system functions
598	20.4 Timescale system tasks
601	20.5 Conversion functions
602	20.6 Data query functions
604	20.7 Array querying functions
606	20.8 Math functions
608	20.9 Bit vector system functions
609	20.10 Severity tasks
610	20.11 Elaboration system tasks
611	20.12 Assertion control system tasks
618	20.13 Sampled value system functions
619	20.14 Coverage system functions 20.15 Probabilistic distribution functions
621	20.16 Stochastic analysis tasks and functions
623	20.17 Programmable logic array modeling system tasks
626	20.18 Miscellaneous tasks and functions
628	21. Input/output system tasks and system functions 21.1 General 21.2 Display system tasks
639	21.3 File input/output system tasks and system functions
649	21.4 Loading memory array data from a file
653	21.5 Writing memory array data to a file
654	21.6 Command line input
657	21.7 Value change dump (VCD) files
678	22. Compiler directives 22.1 General 22.2 Overview 22.3 `resetall
679	22.4 `include 22.5 `define, `undef, and `undefineall
685	22.6 `ifdef, `else, `elsif, `endif, `ifndef
688	22.7 `timescale
689	22.8 `default_nettype
690	22.9 `unconnected_drive and `nounconnected_drive 22.10 `celldefine and `endcelldefine 22.11 `pragma
691	22.12 `line
692	22.13 `__FILE__ and `__LINE__
693	22.14 `begin_keywords, `end_keywords
699	Part Two: Hierarchy Constructs
700	23. Modules and hierarchy 23.1 General 23.2 Module definitions
712	23.3 Module instances (hierarchy)
723	23.4 Nested modules
724	23.5 Extern modules
725	23.6 Hierarchical names
728	23.7 Member selects and hierarchical names
729	23.8 Upwards name referencing
732	23.9 Scope rules
734	23.10 Overriding module parameters
741	23.11 Binding auxiliary code to scopes or instances
745	24. Programs 24.1 General 24.2 Overview 24.3 The program construct
749	24.4 Eliminating testbench races 24.5 Blocking tasks in cycle/event mode
750	24.6 Programwide space and anonymous programs 24.7 Program control tasks
751	25. Interfaces 25.1 General 25.2 Overview
752	25.3 Interface syntax
756	25.4 Ports in interfaces
757	25.5 Modports
763	25.6 Interfaces and specify blocks
764	25.7 Tasks and functions in interfaces
770	25.8 Parameterized interfaces
772	25.9 Virtual interfaces
777	25.10 Access to interface objects
778	26. Packages 26.1 General 26.2 Package declarations
779	26.3 Referencing data in packages
783	26.4 Using packages in module headers
784	26.5 Search order rules
786	26.6 Exporting imported names from packages
787	26.7 The std built-in package
789	27. Generate constructs 27.1 General 27.2 Overview 27.3 Generate construct syntax
791	27.4 Loop generate constructs
795	27.5 Conditional generate constructs
798	27.6 External names for unnamed generate blocks
800	28. Gate-level and switch-level modeling 28.1 General 28.2 Overview 28.3 Gate and switch declaration syntax
806	28.4 and, nand, nor, or, xor, and xnor gates
807	28.5 buf and not gates
808	28.6 bufif1, bufif0, notif1, and notif0 gates
809	28.7 MOS switches
810	28.8 Bidirectional pass switches
811	28.9 CMOS switches
812	28.10 pullup and pulldown sources 28.11 Logic strength modeling
814	28.12 Strengths and values of combined signals
826	28.13 Strength reduction by nonresistive devices 28.14 Strength reduction by resistive devices 28.15 Strengths of net types
827	28.16 Gate and net delays
831	29. User-defined primitives 29.1 General 29.2 Overview 29.3 UDP definition
835	29.4 Combinational UDPs
836	29.5 Level-sensitive sequential UDPs 29.6 Edge-sensitive sequential UDPs
837	29.7 Sequential UDP initialization
839	29.8 UDP instances
840	29.9 Mixing level-sensitive and edge-sensitive descriptions
841	29.10 Level-sensitive dominance
842	30. Specify blocks 30.1 General 30.2 Overview 30.3 Specify block declaration
843	30.4 Module path declarations
852	30.5 Assigning delays to module paths
856	30.6 Mixing module path delays and distributed delays
857	30.7 Detailed control of pulse filtering behavior
866	31. Timing checks 31.1 General 31.2 Overview
869	31.3 Timing checks using a stability window
876	31.4 Timing checks for clock and control signals
885	31.5 Edge-control specifiers
886	31.6 Notifiers: user-defined responses to timing violations
888	31.7 Enabling timing checks with conditioned events
889	31.8 Vector signals in timing checks
890	31.9 Negative timing checks
895	32. Backannotation using the standard delay format 32.1 General 32.2 Overview 32.3 The SDF annotator 32.4 Mapping of SDF constructs to SystemVerilog
900	32.5 Multiple annotations
901	32.6 Multiple SDF files 32.7 Pulse limit annotation
902	32.8 SDF to SystemVerilog delay value mapping
903	32.9 Loading timing data from an SDF file
905	33. Configuring the contents of a design 33.1 General 33.2 Overview
906	33.3 Libraries
908	33.4 Configurations
914	33.5 Using libraries and configs
915	33.6 Configuration examples
917	33.7 Displaying library binding information 33.8 Library mapping examples
920	34. Protected envelopes 34.1 General 34.2 Overview 34.3 Processing protected envelopes
922	34.4 Protect pragma directives
924	34.5 Protect pragma keywords
940	Part Three: Application Programming Interfaces
941	35. Direct programming interface 35.1 General 35.2 Overview
942	35.3 Two layers of DPI
943	35.4 Global name space of imported and exported functions
944	35.5 Imported tasks and functions
951	35.6 Calling imported functions
953	35.7 Exported functions
954	35.8 Exported tasks 35.9 Disabling DPI tasks and functions
956	36. Programming language interface (PLI/VPI) overview 36.1 General 36.2 PLI purpose and history
957	36.3 User-defined system task and system function names
958	36.4 User-defined system task and system function arguments 36.5 User-defined system task and system function types 36.6 User-supplied PLI applications 36.7 PLI include files 36.8 VPI sizetf, compiletf, and calltf routines
959	36.9 PLI mechanism
961	36.10 VPI access to SystemVerilog objects and simulation objects
962	36.11 List of VPI routines by functional category
964	36.12 VPI backwards compatibility features and limitations
969	37. VPI object model diagrams 37.1 General 37.2 VPI Handles
970	37.3 VPI object classifications
976	37.4 Key to data model diagrams
979	37.5 Module
980	37.6 Interface 37.7 Modport 37.8 Interface task or function declaration
981	37.9 Program
982	37.10 Instance
984	37.11 Instance arrays
985	37.12 Scope
986	37.13 IO declaration
987	37.14 Ports
988	37.15 Reference objects
990	37.16 Nets
994	37.17 Variables
997	37.18 Packed array variables
998	37.19 Variable select
999	37.20 Memory 37.21 Variable drivers and loads
1000	37.22 Object Range
1001	37.23 Typespec
1003	37.24 Structures and unions
1004	37.25 Named events
1005	37.26 Parameter, spec param, def param, param assign
1006	37.27 Virtual interface
1008	37.28 Interface typespec
1009	37.29 Class definition
1010	37.30 Class typespec
1012	37.31 Class variables and class objects
1014	37.32 Constraint, constraint ordering, distribution
1015	37.33 Primitive, prim term
1016	37.34 UDP 37.35 Intermodule path
1017	37.36 Constraint expression
1018	37.37 Module path, path term
1019	37.38 Timing check
1020	37.39 Task and function declaration
1021	37.40 Task and function call
1023	37.41 Frames
1024	37.42 Threads 37.43 Delay terminals
1025	37.44 Net drivers and loads
1026	37.45 Continuous assignment
1027	37.46 Clocking block
1028	37.47 Assertion
1029	37.48 Concurrent assertions
1030	37.49 Property declaration
1031	37.50 Property specification
1032	37.51 Sequence declaration
1033	37.52 Sequence expression
1034	37.53 Immediate assertions
1035	37.54 Multiclock sequence expression 37.55 Let
1036	37.56 Simple expressions
1037	37.57 Expressions
1040	37.58 Atomic statement
1041	37.59 Dynamic prefixing
1042	37.60 Event statement 37.61 Process
1043	37.62 Assignment 37.63 Event control
1044	37.64 While, repeat 37.65 Waits 37.66 Delay control
1045	37.67 Repeat control 37.68 Forever 37.69 If, if–else
1046	37.70 Case, pattern
1047	37.71 Expect 37.72 For 37.73 Do-while, foreach
1048	37.74 Alias statement 37.75 Disables 37.76 Return statement
1049	37.77 Assign statement, deassign, force, release 37.78 Callback
1050	37.79 Time queue 37.80 Active time format
1051	37.81 Attribute
1052	37.82 Iterator
1053	37.83 Generates
1055	38. VPI routine definitions 38.1 General 38.2 vpi_chk_error()
1056	38.3 vpi_compare_objects()
1058	38.4 vpi_control()
1059	38.5 vpi_flush() 38.6 vpi_get()
1060	38.7 vpi_get64() 38.8 vpi_get_cb_info()
1061	38.9 vpi_get_data()
1062	38.10 vpi_get_delays()
1064	38.11 vpi_get_str()
1065	38.12 vpi_get_systf_info()
1066	38.13 vpi_get_time()
1067	38.14 vpi_get_userdata() 38.15 vpi_get_value()
1073	38.16 vpi_get_value_array()
1077	38.17 vpi_get_vlog_info()
1078	38.18 vpi_handle()
1079	38.19 vpi_handle_by_index() 38.20 vpi_handle_by_multi_index()
1080	38.21 vpi_handle_by_name()
1081	38.22 vpi_handle_multi() 38.23 vpi_iterate()
1082	38.24 vpi_mcd_close()
1083	38.25 vpi_mcd_flush() 38.26 vpi_mcd_name()
1084	38.27 vpi_mcd_open()
1085	38.28 vpi_mcd_printf()
1086	38.29 vpi_mcd_vprintf() 38.30 vpi_printf()
1087	38.31 vpi_put_data()
1089	38.32 vpi_put_delays()
1092	38.33 vpi_put_userdata() 38.34 vpi_put_value()
1095	38.35 vpi_put_value_array()
1099	38.36 vpi_register_cb()
1107	38.37 vpi_register_systf()
1111	38.38 vpi_release_handle() 38.39 vpi_remove_cb()
1112	38.40 vpi_scan()
1113	38.41 vpi_vprintf()
1114	39. Assertion API 39.1 General 39.2 Overview 39.3 Static information
1115	39.4 Dynamic information
1119	39.5 Control functions
1123	40. Code coverage control and API 40.1 General 40.2 Overview
1124	40.3 SystemVerilog real-time coverage access
1129	40.4 FSM recognition
1132	40.5 VPI coverage extensions
1137	41. Data read API
1138	Part Four: Annexes
1139	Annex A (normative) Formal syntax A.1 Source text
1148	A.2 Declarations
1159	A.3 Primitive instances
1160	A.4 Instantiations
1162	A.5 UDP declaration and instantiation
1163	A.6 Behavioral statements
1170	A.7 Specify section
1174	A.8 Expressions
1179	A.9 General
1182	A.10 Footnotes (normative)
1185	Annex B (normative) Keywords
1187	Annex C (normative) Deprecation C.1 General C.2 Constructs that have been deprecated
1188	C.3 Accellera SystemVerilog 3.1a-compatible access to packed data C.4 Constructs identified for deprecation
1191	Annex D (informative) Optional system tasks and system functions D.1 General D.2 $countdrivers
1192	D.3 $getpattern
1193	D.4 $input D.5 $key and $nokey D.6 $list D.7 $log and $nolog
1194	D.8 $reset, $reset_count, and $reset_value
1195	D.9 $save, $restart, and $incsave
1196	D.10 $scale D.11 $scope D.12 $showscopes D.13 $showvars D.14 $sreadmemb and $sreadmemh
1198	Annex E (informative) Optional compiler directives E.1 General E.2 `default_decay_time E.3 `default_trireg_strength
1199	E.4 `delay_mode_distributed E.5 `delay_mode_path E.6 `delay_mode_unit E.7 `delay_mode_zero
1200	Annex F (normative) Formal semantics of concurrent assertions F.1 General F.2 Overview
1201	F.3 Abstract syntax
1207	F.4 Rewriting algorithms
1211	F.5 Semantics
1220	F.6 Extended expressions F.7 Recursive properties
1222	Annex G (normative) Std package G.1 General G.2 Overview G.3 Semaphore G.4 Mailbox
1223	G.5 Randomize G.6 Process
1224	Annex H (normative) DPI C layer H.1 General H.2 Overview
1225	H.3 Naming conventions H.4 Portability H.5 svdpi.h include file
1226	H.6 Semantic constraints
1228	H.7 Data types
1232	H.8 Argument passing modes
1235	H.9 Context tasks and functions
1239	H.10 Include files
1242	H.11 Arrays
1245	H.12 Open arrays
1251	H.13 SV3.1a-compatible access to packed data (deprecated functionality)
1257	Annex I (normative) svdpi.h I.1 General I.2 Overview I.3 Source code
1266	Annex J (normative) Inclusion of foreign language code J.1 General J.2 Overview
1267	J.3 Location independence J.4 Object code inclusion
1270	Annex K (normative) vpi_user.h K.1 General K.2 Source code
1287	Annex L (normative) vpi_compatibility.h L.1 General L.2 Source code
1290	Annex M (normative) sv_vpi_user.h M.1 General M.2 Source code
1300	Annex N (normative) Algorithm for probabilistic distribution functions N.1 General N.2 Source code
1308	Annex O (informative) Encryption/decryption flow O.1 General O.2 Overview O.3 Tool vendor secret key encryption system
1309	O.4 IP author secret key encryption system
1310	O.5 Digital envelopes
1312	Annex P (informative) Glossary
1315	Annex Q (informative) Bibliography

Additional information

Standard Title	IEEE Standard for SystemVerilog–Unified Hardware Design, Specification, and Verification Language
Published Code	IEEE
Publication Date	2012
Pages Count	1315

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