IEEE 1801-2009

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IEEE Standard for Design and Verification of Low Power Integrated Circuits

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IEEE	2009

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Description

New IEEE Standard – Superseded. The power supplied to elements in an electronic design affects the way circuits operate. Although this is obvious when stated, today’s set of high-level design languages have not had a consistent way to concisely represent the regions of a design with different power provisions, nor the states of those regions or domains. This standard provides an HDL-independent way of annotating a design with power intent. In addition, the level-shifting and isolation between power domains may be described for a specific implementation, from high-level constraints to particular configurations. When the logic in a power domain receives different power supply levels, the logic state of portions of the design may be preserved with various state-retention strategies. This standard provides mechanisms for the refined and specific description of intent, effect, and implementation of various retention strategies. Incorporating components into designs is greatly assisted by the encapsulation and specification of the characteristics of the power environment of the design and the power requirements and capabilities of the components; this information encapsulation mechanism is also described in this standard. The analysis of the various power modes of a design is enabled with a combination of the description of the power modes and the collection, generation, and propagation of switching information.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Standard for Design and Verification of Low Power Integrated Circuits
3	IEEE Std 1801-2009 title page
6	Introduction
7	Notice to users Copyrights Updating of IEEE documents Errata
8	Interpretations Patents
9	Participants
11	CONTENTS
17	Important Notice 1. Overview 1.1 Scope 1.2 Purpose 1.3 Key characteristics of the Unified Power Format (UPF)
19	1.4 Power supply network design intent
21	1.5 Extending logic specification
22	1.6 Conventions used
23	1.7 Use of color in this standard 1.8 Contents of this standard
25	2. Normative references 3. Definitions, acronyms, and abbreviations 3.1 Definitions
28	3.2 Acronyms and abbreviations
31	4. Power domains, supply sets, name spaces, and precedence 4.1 Power domains
32	4.2 Supply nets and ports 4.3 Supply sets
33	4.3.1 Explicit connection of supply nets 4.3.2 Automatic connection of supply nets 4.3.3 Implicit connection of supply nets
34	4.3.4 Predefined supply set functions 4.4 Naming rules
35	4.5 Name space semantics
36	4.6 Attributes and HDLs
37	4.7 Precedence 4.8 Lexical elements 4.9 Units
38	4.10 Boolean expressions
39	5. Simulation semantics 5.1 Supply network creation 5.2 Supply network simulation semantics 5.2.1 Supply network initialization
40	5.2.2 Supply network update and evaluation 5.3 Power switch modeling
42	5.4 Power states 5.4.1 Power states of supply nets and ports 5.4.2 Power states of supply sets
43	5.4.3 Power states of power domains
47	5.4.4 Power states of systems and subsystems
48	5.5 Power state name spaces 5.6 Simstate simulation semantics
49	5.6.1 NORMAL 5.6.2 CORRUPT 5.6.3 CORRUPT_ON_ACTIVITY 5.6.4 CORRUPT_STATE_ON_CHANGE
50	5.6.5 CORRUPT_STATE_ON_ACTIVITY 5.6.6 NOT_NORMAL 5.7 Transitioning from one simstate state to another 5.7.1 Any state transition to CORRUPT 5.7.2 Any state transition to CORRUPT_ON_ACTIVITY 5.7.3 Any state transition to CORRUPT_STATE_ON_CHANGE
51	5.7.4 Any state transition to CORRUPT_STATE_ON_ACTIVITY 5.7.5 Any state transition to NORMAL 5.7.6 Any state transition to NOT_NORMAL
53	6. Commands 6.1 Conventions used
54	6.2 Generic UPF command semantics 6.3 effective_element_list semantics
55	6.3.1 Transitive TRUE
56	6.3.2 Result
57	6.4 Command refinement
58	6.5 Error handling 6.5.1 errorCode
59	6.5.2 errorInfo 6.6 add_domain_elements
60	6.7 add_port_state
61	6.8 add_power_state
63	6.9 add_pst_state
64	6.10 associate_supply_set
66	6.11 bind_checker
67	6.12 connect_logic_net
68	6.13 connect_supply_net
69	6.14 connect_supply_set
71	6.15 create_composite_domain
72	6.16 create_hdl2upf_vct
74	6.17 create_logic_net 6.18 create_logic_port
75	6.19 create_power_domain
77	6.20 create_power_switch
80	6.21 create_pst
81	6.22 create_supply_net 6.22.1 Supply net resolution
82	6.22.2 Resolutions methods
83	6.22.3 Supply nets defined in HDL 6.23 create_supply_port
84	6.24 create_supply_set
85	6.24.1 Predefined supply set functions 6.24.2 Referencing supply set functions
86	6.25 create_upf2hdl_vct
87	6.26 describe_state_transition
88	6.27 load_simstate_behavior 6.28 load_upf
89	6.29 load_upf_protected
90	6.30 map_isolation_cell
92	6.31 map_level_shifter_cell
93	6.32 map_power_switch
94	6.33 map_retention_cell
97	6.34 merge_power_domains
99	6.35 name_format
100	6.36 save_upf
101	6.37 set_design_attributes
102	6.38 set_design_top 6.39 set_domain_supply_net
104	6.40 set_isolation
110	6.41 set_isolation_control
111	6.42 set_level_shifter
116	6.43 set_partial_on_translation
117	6.44 set_pin_related_supply
118	6.45 set_port_attributes
122	6.46 set_power_switch
124	6.47 set_retention
128	6.48 set_retention_control
130	6.49 set_retention_elements
131	6.50 set_scope 6.51 set_simstate_behavior
132	6.52 upf_version
133	6.53 use_interface_cell
137	7. Queries
138	7.1 find_objects
139	7.1.1 Pattern matching and wildcarding 7.1.2 Wildcarding examples
140	7.2 query_upf
142	7.3 query_associate_supply_set
143	7.4 query_bind_checker
144	7.5 query_cell_instances 7.6 query_cell_mapped
145	7.7 query_composite_domain
146	7.8 query_design_attributes
147	7.9 query_hdl2upf_vct
148	7.10 query_isolation
149	7.11 query_isolation_control
151	7.12 query_level_shifter
152	7.13 query_map_isolation_cell
153	7.14 query_map_level_shifter_cell
154	7.15 query_map_power_switch
155	7.16 query_map_retention_cell
156	7.17 query_name_format
157	7.18 query_net_ports
158	7.19 query_partial_on_translation 7.20 query_pin_related_supply
159	7.21 query_port_attributes
160	7.22 query_port_direction 7.23 query_port_net
161	7.24 query_port_state
162	7.25 query_power_domain
163	7.26 query_power_domain_element 7.27 query_power_state
164	7.28 query_power_switch
165	7.29 query_pst
166	7.30 query_pst_state
167	7.31 query_retention
169	7.32 query_retention_control
170	7.33 query_retention_elements
171	7.34 query_simstate_behavior
172	7.35 query_state_transition
173	7.36 query_supply_net
174	7.37 query_supply_port
175	7.38 query_supply_set
176	7.39 query_upf2hdl_vct
177	7.40 query_use_interface_cell
179	8. Switching Activity Interchange Format (SAIF)
180	8.1 Syntactic conventions
181	8.2 Lexical conventions 8.2.1 White space 8.2.2 Comments 8.2.3 Numbers
182	8.2.4 Strings 8.2.5 Parenthesis 8.2.6 Operators 8.2.7 Hierarchical separator character 8.2.8 Identifiers 8.2.9 Keywords
183	8.2.10 Syntactic categories for token types 8.3 Backward SAIF file
184	8.3.1 SAIF file 8.3.2 Header
187	8.3.3 Simple timing attributes 8.3.4 Simple toggle attributes
189	8.3.5 State-dependent timing attributes
191	8.3.6 State-dependent toggle attributes
193	8.3.7 Path-dependent toggle attributes
194	8.3.8 SDPD toggle attributes 8.3.9 Net, port, and leakage switching specifications
196	8.3.10 Backward SAIF info and instance data
197	8.4 Library forward SAIF file
198	8.4.1 The SAIF file
200	8.4.2 State-dependent timing directive
201	8.4.3 State-dependent toggle directive 8.4.4 Path-dependent toggle directive
202	8.4.5 SDPD toggle directives 8.4.6 Module SDPD declarations
203	8.4.7 Library SDPD information
204	8.5 The RTL forward SAIF file 8.5.1 The SAIF file
206	8.5.2 Port and net mapping directives
207	8.5.3 Instance declarations
209	Annex A (informative) Bibliography
211	Annex B (normative) Supply net logic type B.1 VHDL
217	B.2 SystemVerilog
223	Annex C (normative) Value conversion tables (VCTs) C.1 VHDL_SL2UPF C.2 UPF2VHDL_SL C.3 VHDL_SL2UPF_GNDZERO C.4 UPF_GNDZERO2VHDL_SL
224	C.5 SV_LOGIC2UPF C.6 UPF2SV_LOGIC C.7 SV_LOGIC2UPF_GNDZERO C.8 UPF_GNDZERO2SV_LOGIC C.9 VHDL_TIED_HI
225	C.10 SV_TIED_HI C.11 VHDL_TIED_LO C.12 SV_TIED_LO
227	Annex D (informative) UPF procs
233	Annex E (informative) De-rating factor for inertial glitch