IEEE 1801-2013

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IEEE Standard for Design and Verification of Low-Power Integrated Circuits

Published By	Publication Date	Number of Pages
IEEE	2013	348

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Description

Revision Standard – Superseded. A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows. (Thanks to our sponsor, the PDF of this standard is provided to the public no charge. Visit https://ieeexplore.ieee.org/browse/standards/get-program/page for more details.)

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1801-2013 Front cover
3	Title page
6	Notice to users Laws and regulations Copyrights Updating of IEEE documents Errata Patents
8	Participants
10	Introduction
13	Contents
17	Important notice 1. Overview 1.1 Scope 1.2 Purpose 1.3 Key characteristics of the Unified Power Format
19	1.4 Use of color in this standard 1.5 Contents of this standard
20	2. Normative references 3. Definitions, acronyms, and abbreviations 3.1 Definitions
25	3.2 Acronyms and abbreviations
27	4. UPF concepts 4.1 Design structure 4.1.1 Transistors 4.1.2 Standard cells 4.1.3 Hard macros 4.2 Design representation 4.2.1 Models
28	4.2.2 Netlist 4.2.3 Behavioral models 4.2.4 HDL scopes 4.2.5 Design hierarchy
29	4.2.6 Logic hierarchy 4.2.7 Hierarchy navigation
30	4.2.8 Ports and nets 4.2.9 Connecting nets to ports 4.3 Power architecture
31	4.3.1 Power domains 4.3.2 Drivers, receivers, sources, and sinks
32	4.3.3 Isolation and level-shifting
33	4.3.4 State retention 4.4 Power distribution
34	4.4.1 Supply network elements
35	4.4.2 Supply network construction
37	4.4.3 Supply equivalence
39	4.5 Power management 4.5.1 Related supplies 4.5.2 Driver and receiver supplies
40	4.5.3 Logic sources and sinks 4.5.4 Power-management requirements
41	4.5.5 Power-management strategies 4.5.6 Power-management implementation
42	4.5.7 Power control logic 4.6 Power states 4.6.1 Power state of a supply port or supply net 4.6.2 Power state of a supply set
43	4.6.3 Predefined supply set power states 4.6.4 Power states of power domains
44	4.6.5 Power states of systems and subsystems 4.6.6 Incremental refinement of power states
45	4.7 Simstates
46	4.8 Successive refinement
47	4.9 Tool flow
48	4.10 File structure
49	5. Language basics 5.1 UPF is Tcl 5.2 Conventions used
50	5.3 Lexical elements
51	5.3.1 Identifiers 5.3.2 Keywords and reserved words 5.3.3 Names
53	5.3.4 Lists and strings 5.3.5 Special characters 5.4 Boolean expressions
55	5.5 Object declaration
56	5.6 Attributes of objects
59	5.7 Power state name spaces
60	5.8 Precedence
61	5.9 Generic UPF command semantics 5.10 effective_element_list semantics
62	5.10.1 Transitive TRUE
63	5.10.2 Result
64	5.11 Command refinement
65	5.12 Error handling
66	5.12.1 errorCode 5.12.2 errorInfo 5.13 Units
67	6. Power intent commands 6.1 Categories 6.2 add_domain_elements [deprecated]
68	6.3 add_port_state [legacy] 6.4 add_power_state
73	6.5 add_pst_state [legacy]
74	6.6 apply_power_model
75	6.7 associate_supply_set
76	6.8 begin_power_model
77	6.9 bind_checker
79	6.10 connect_logic_net
80	6.11 connect_supply_net
81	6.12 connect_supply_set
83	6.13 create_composite_domain
84	6.14 create_hdl2upf_vct
85	6.15 create_logic_net
86	6.16 create_logic_port
87	6.17 create_power_domain
90	6.18 create_power_switch
96	6.19 create_pst [legacy] 6.20 create_supply_net
97	6.20.1 Supply net resolution 6.20.2 Resolutions methods
98	6.20.3 Supply nets defined in HDL
99	6.21 create_supply_port
100	6.22 create_supply_set
101	6.22.1 Referencing supply set functions 6.22.2 Implicit supply net 6.23 create_upf2hdl_vct
102	6.24 describe_state_transition
103	6.25 end_power_model
104	6.26 find_objects
105	6.26.1 Pattern matching and wildcarding 6.26.2 Wildcarding examples
106	6.27 load_simstate_behavior
107	6.28 load_upf
108	6.29 load_upf_protected
109	6.30 map_isolation_cell [deprecated] 6.31 map_level_shifter_cell [deprecated] 6.32 map_power_switch
110	6.33 map_retention_cell
113	6.34 merge_power_domains [deprecated]
114	6.35 name_format
115	6.36 save_upf
116	6.37 set_design_attributes
117	6.38 set_design_top 6.39 set_domain_supply_net [legacy]
118	6.40 set_equivalent
120	6.41 set_isolation
126	6.42 set_isolation_control [deprecated]
127	6.43 set_level_shifter
132	6.44 set_partial_on_translation 6.45 set_pin_related_supply [deprecated]
133	6.46 set_port_attributes
137	6.47 set_power_switch [deprecated] 6.48 set_repeater
140	6.49 set_retention
144	6.50 set_retention_control [deprecated] 6.51 set_retention_elements
145	6.52 set_scope
146	6.53 set_simstate_behavior
147	6.54 upf_version
148	6.55 use_interface_cell
151	7. Power management cell commands 7.1 Introduction
152	7.2 define_always_on_cell
153	7.3 define_diode_clamp
154	7.4 define_isolation_cell
157	7.5 define_level_shifter_cell
161	7.6 define_power_switch_cell
163	7.7 define_retention_cell
166	8. UPF processing 8.1 Overview 8.2 Data requirements 8.3 Processing phases
167	8.3.1 Phase 1—read and resolve UPF specification 8.3.2 Phase 2—build power intent model
168	8.3.3 Phase 3—recognize implemented power intent
169	8.3.4 Phase 4—apply power intent model to design 8.4 Error checking
170	9. Simulation semantics 9.1 Supply network creation
171	9.2 Supply network simulation 9.2.1 Supply network initialization
172	9.2.2 Power-switch evaluation
173	9.2.3 Supply network evaluation 9.3 Power state simulation 9.3.1 Power state control
174	9.3.2 Power state determination
175	9.4 Simstate simulation
176	9.4.1 NORMAL 9.4.2 CORRUPT 9.4.3 CORRUPT_ON_ACTIVITY 9.4.4 CORRUPT_ON_CHANGE
177	9.4.5 CORRUPT_STATE_ON_CHANGE 9.4.6 CORRUPT_STATE_ON_ACTIVITY 9.4.7 NOT_NORMAL 9.5 Transitioning from one simstate state to another 9.5.1 Any state transition to CORRUPT
178	9.5.2 Any state transition to CORRUPT_ON_ACTIVITY 9.5.3 Any state transition to CORRUPT_ON_CHANGE 9.5.4 Any state transition to CORRUPT_STATE_ON_CHANGE 9.5.5 Any state transition to CORRUPT_STATE_ON_ACTIVITY 9.5.6 Any state transition to NORMAL 9.5.7 Any state transition to NOT_NORMAL 9.6 Simulation of retention
179	9.6.1 Retention corruption summary
180	9.6.2 Retention modeling for different retention styles
184	9.7 Simulation of isolation 9.8 Simulation of level-shifting 9.9 Simulation of repeater
185	Annex A (informative) Bibliography
186	Annex B (normative) HDL package UPF B.1 Supply net logic type values B.2 Path names B.3 VHDL UPF package
191	B.4 SystemVerilog UPF package
198	Annex C (normative) Queries
199	C.1 query_upf
201	C.2 query_associate_supply_set
202	C.3 query_bind_checker
203	C.4 query_cell_instances C.5 query_cell_mapped
204	C.6 query_composite_domain
205	C.7 query_design_attributes
206	C.8 query_hdl2upf_vct
207	C.9 query_isolation
208	C.10 query_isolation_control [deprecated]
209	C.11 query_level_shifter
210	C.12 query_map_isolation_cell [deprecated] C.13 query_map_level_shifter_cell [deprecated]
211	C.14 query_map_power_switch
212	C.15 query_map_retention_cell
213	C.16 query_name_format
214	C.17 query_net_ports C.18 query_partial_on_translation
215	C.19 query_pin_related_supply [deprecated] C.20 query_port_attributes
216	C.21 query_port_direction C.22 query_port_net
217	C.23 query_port_state
218	C.24 query_power_domain
219	C.25 query_power_domain_element C.26 query_power_state
220	C.27 query_power_switch
222	C.28 query_pst [legacy]
223	C.29 query_pst_state [legacy]
224	C.30 query_retention
225	C.31 query_retention_control [deprecated] C.32 query_retention_elements
226	C.33 query_simstate_behavior
228	C.34 query_state_transition
229	C.35 query_supply_net
230	C.36 query_supply_port
231	C.37 query_supply_set
232	C.38 query_upf2hdl_vct
233	C.39 query_use_interface_cell
235	Annex D (informative) Replacing deprecated and legacy commands and options D.1 Deprecated and legacy constructs
238	D.2 Recommendations for replacing deprecated and legacy constructs
243	Annex E (informative) Low-power design methodology E.1 Design, implementation, and verification flow for a soft IP
245	E.2 RTL design stage
255	E.3 Logic implementation
259	E.4 Physical implementation
263	E.5 SoC integration flow E.6 How to create a configuration UPF
268	Annex F (normative) Value conversion tables F.1 VHDL_SL2UPF F.2 UPF2VHDL_SL F.3 VHDL_SL2UPF_GNDZERO
269	F.4 UPF_GNDZERO2VHDL_SL F.5 SV_LOGIC2UPF F.6 UPF2SV_LOGIC F.7 SV_LOGIC2UPF_GNDZERO F.8 UPF_GNDZERO2SV_LOGIC
270	F.9 VHDL_TIED_HI F.10 SV_TIED_HI F.11 VHDL_TIED_LO F.12 SV_TIED_LO
271	Annex G (normative) Supporting hard IP G.1 Attributing feedthrough ports of hard IP
272	G.2 Attributing unconnected ports of hard IP
274	Annex H (normative) UPF power-management commands semantics and Liberty mappings H.1 Introduction H.2 define_always_on_cell
276	H.3 define_diode_clamp
277	H.4 define_isolation_cell
280	H.5 define_level_shifter_cell
283	H.6 define_power_switch_cell
285	H.7 define_retention_cell
289	Annex I (informative) Power-management cell modeling examples I.1 Modeling always-on cells
292	I.2 Modeling cells with internal diodes
293	I.3 Modeling isolation cells
301	I.4 Modeling level-shifters
309	I.5 Modeling power-switch cells
313	I.6 Modeling state retention cells
319	Annex J (normative) Switching Activity Interchange Format
320	J.1 Syntactic conventions
321	J.2 Lexical conventions
323	J.3 Backward SAIF file
338	J.4 Library forward SAIF file
345	J.5 RTL forward SAIF file