IEEE 696 1983

$18.96

IEEE Standard 696 Interface Devices

Published By	Publication Date	Number of Pages
IEEE	1983	40

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Description

New IEEE Standard – Inactive – Withdrawn. This standard applies to interface systems for computer system components interconnected by way of a 100-line parallel backplane commonly known as the S-100 bus. It applies to microprocessor computer systems, or portions of them, where: (1) Data exchanged among the interconnected devices is digital. (2) A maximum of 22 devices are interconnected. (3) The total transmission path length among interconnected devices is less than or equal to 25 in (63.5 cm). (4) The maximum switching rate of any signal on the bus is less than or equal to 6 MHz Withdrawn standard

PDF Catalog

PDF Pages	PDF Title
8	General 1.1 Scope 1.2 Object 1.3 Definitions 1.3.1 General-System Terms 1.3.2 Signals and Paths
9	State Diagram Notation
10	1.5 Logical and Electrical State Relationships Table 1 Active High Signals Table2 ActiveLowSignals
11	Interface System Overview Interface System Objective Fundamental Communication Capabilities 1.6.3 Message Paths and Bus Structure Functional Specifications 2.1 Functional Partition Table 3 Bus Structures
12	2.2 SignalLines 2.2.1 General 2.2.2 Address Bus Table 4 Address Usage for Different Bus Cycles Fig
13	2.2.3 Status Bus Table 5 Status Usage Chart Fig
14	2.2.4 DataBus Control Output Bus 2.2.6 Control Input Bus
15	Table 6 IEEE Std 696 Bus Pin List
18	2.2.7 TMA Control Bus 2.2.8 Vectored Interrupt Bus 2.2.9 System Utilities
19	2.2.10 PinList 2.3 The Permanent Master Interface 2.3.1 General
20	Permanent Master State Diagram 2.3.3 Permanent Master State Descriptions Permanent Master State Diagram
21	Required Signals for Permanent Masters 2.3.5 Dummy Mastering The Temporary Master Interface 2.4.1 General Temporary Master State Diagram Temporary Master State Descriptions Temporary Master State Diagram
22	Required Signals For Temporary Masters 2.5 The Slave Interface 2.5.1 Slave-Interface State Diagram 2.5.2 Slave-State Definitions Slave Interface State Diagram
23	Required Signals for Slave Interfaces 2.6 8/16-bit Data Transfer Control 2.6.1 General 2.6.2 8-bit Data Paths 2.6.3 l6-bit Data Paths 2.6.4 Memory Organization
24	8/16 Bit-Memory Organization 8/16 Bit Address + Data Usage
25	2.6.5 Sixteen Acknowledge (SIXTN*) 2.7 Fundamental Bus-Cycle Timing 2.7.1 General 2.7.2 Address and Status Buses Bus-Cycle Fundamental Timing Relationships
26	2.7.3 Ready and Sixteen Acknowledge Lines 2.7.4 Read Cycles 2.7.5 Writecycles
27	Special Bus Operations 2.8.1 General 2.8.2 Bus Transfer Protocol Bus-Transfer State Diagram
28	TMATiming Table 7 Control Output Line Levels
29	2.8.3 Bus Arbitration Protocol Arbitration Diagram
30	Bus Arbitration Example
31	Bus Arbitration Timing Diagrams
32	2.8.4 Summary of Arbitration Protocol 2.9 Interrupt Protocol 2.9.1 Vectored Interrupts
33	Nonmaskable Interrupt (NMI) 2.10 Special Condition Lines 2.10.1 Power-fail Pending (PWRFAIL”) 2.10.2 ERROR 3 Electrical Specifications 3.1 Application 3.2 PowerDistribution 3.2.1 +8 V Specification 3.2.2 +16 V Specification 3.2.3 – 3.2.3 – 16 V Specification
34	3.3 General Signal Discipline 3.4 Driver Requirements 3.4.1 Driver Types 3.4.2 Driver Specifications 3.5 Receiver Specifications 3.6 Bidirectional Signals 3.7 Card-Level Bus Loading Read Cycle Timing Specification Write-Cycle Timing Specification
35	Read-Cycle Timing Diagram Write-Cycle Timing Diagram
36	Table 8 Read and Write Cycle Timing Parameters
37	3.10 Ready and Sixteen Request Timing Specification 3.1 1 Bus Transfer Timing Specification 3.12 PHANTOM* Timing Specification Timing of RDY XRDY and SIXTN* During Read and Write Cycles Overlap of PHANTOM* and Read and Write Strobes Table 9 Bus Transfer Timing Parameters
38	Mechanical Specifications 4.1 Application 4.2 ConnectorType 4.2.1 Electrical Considerations 4.2.2 Connector Spacing 4.3 Board Size Specification Fig 16 IEEE Std 696 Board Mechanical Parameters
40	Quick Reference IEEE Std 696 Bus Layout