IEEE 802.3-2015

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IEEE Standard for Ethernet

Published By	Publication Date	Number of Pages
IEEE	2015

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Description

Revision Standard – Superseded. Ethernet local area network operation is specified for selected speeds of operation from 1 Mb/s to 100 Gb/s using a common media access control (MAC) specification and management information base (MIB). The Carrier Sense Multiple Access with Collision Detection (CSMA/CD) MAC protocol specifies shared medium (half duplex) operation, as well as full duplex operation. Speed specific Media Independent Interfaces (MIIs) allow use of selected Physical Layer devices (PHY) for operation over coaxial, twisted pair or fiber optic cables, or electrical backplanes. System considerations for multisegment shared access networks describe the use of Repeaters which are defined for operational speeds up to 1000 Mb/s. Local Area Network (LAN) operation is supported at all speeds. Other specified capabilities include: various PHY types for access networks, PHYs suitable for metropolitan area network applications, and the provision of power over selected twisted pair PHY types.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Standard for Ethernet SECTION FOUR Contents
38	44. Introduction to 10 Gb/s baseband network 44.1 Overview 44.1.1 Scope 44.1.2 Objectives 44.1.3 Relationship of 10 Gigabit Ethernet to the ISO OSI reference model
39	44.1.4 Summary of 10 Gigabit Ethernet sublayers 44.1.4.1 Reconciliation Sublayer (RS) and 10 Gigabit Media Independent Interface (XGMII)
40	44.1.4.2 XGMII Extender Sublayer (XGXS) and 10 Gigabit Attachment Unit Interface (XAUI) 44.1.4.3 Management interface (MDIO/MDC) 44.1.4.4 Physical Layer signaling systems
41	44.1.4.5 WAN Interface Sublayer (WIS), type 10GBASE-W 44.1.5 Management 44.2 State diagrams 44.3 Delay constraints
43	44.4 Protocol implementation conformance statement (PICS) proforma
44	45. Management Data Input/Output (MDIO) Interface 45.1 Overview 45.1.1 Summary of major concepts 45.1.2 Application
45	45.2 MDIO Interface Registers
48	45.2.1 PMA/PMD registers
53	45.2.1.1 PMA/PMD control 1 register (Register 1.0)
54	45.2.1.1.1 Reset (1.0.15) 45.2.1.1.2 Low power (1.0.11) 45.2.1.1.3 Speed selection (1.0.13, 1.0.6, 1.0.5:2)
55	45.2.1.1.4 PMA remote loopback (1.0.1) 45.2.1.1.5 PMA local loopback (1.0.0) 45.2.1.2 PMA/PMD status 1 register (Register 1.1)
56	45.2.1.2.1 PMA ingress AUI stop ability (1.1.9) 45.2.1.2.2 PMA egress AUI stop ability (1.1.8) 45.2.1.2.3 Fault (1.1.7) 45.2.1.2.4 Receive link status (1.1.2)
57	45.2.1.2.5 Low-power ability (1.1.1) 45.2.1.3 PMA/PMD device identifier (Registers 1.2 and 1.3) 45.2.1.4 PMA/PMD speed ability (Register 1.4)
58	45.2.1.4.1 100G capable (1.4.9) 45.2.1.4.2 40G capable (1.4.8) 45.2.1.4.3 10/1G capable (1.4.7) 45.2.1.4.4 10M capable (1.4.6) 45.2.1.4.5 100M capable (1.4.5) 45.2.1.4.6 1000M capable (1.4.4) 45.2.1.4.7 10PASS-TS capable (1.4.2) 45.2.1.4.8 2BASE-TL capable (1.4.1)
59	45.2.1.4.9 10G capable (1.4.0) 45.2.1.5 PMA/PMD devices in package (Registers 1.5 and 1.6) 45.2.1.6 PMA/PMD control 2 register (Register 1.7) 45.2.1.6.1 PMA ingress AUI stop enable (1.7.9) 45.2.1.6.2 PMA egress AUI stop enable (1.7.8) 45.2.1.6.3 PMA/PMD type selection (1.7.5:0) 45.2.1.7 PMA/PMD status 2 register (Register 1.8) 45.2.1.7.1 Device present (1.8.15:14) 45.2.1.7.2 Transmit fault ability (1.8.13)
61	45.2.1.7.3 Receive fault ability (1.8.12)
62	45.2.1.7.4 Transmit fault (1.8.11) 45.2.1.7.5 Receive fault (1.8.10)
63	45.2.1.7.6 PMA/PMD extended abilities (1.8.9) 45.2.1.7.7 PMD transmit disable ability (1.8.8)
64	45.2.1.7.8 10GBASE-SR ability (1.8.7) 45.2.1.7.9 10GBASE-LR ability (1.8.6) 45.2.1.7.10 10GBASE-ER ability (1.8.5) 45.2.1.7.11 10GBASE-LX4 ability (1.8.4) 45.2.1.7.12 10GBASE-SW ability (1.8.3) 45.2.1.7.13 10GBASE-LW ability (1.8.2) 45.2.1.7.14 10GBASE-EW ability (1.8.1) 45.2.1.7.15 PMA local loopback ability (1.8.0) 45.2.1.8 PMD transmit disable register (Register 1.9)
65	45.2.1.8.1 PMD transmit disable 9 (1.9.10)
66	45.2.1.8.2 PMD transmit disable 4, 5, 6, 7, 8 (1.9.5, 1.9.6, 1.9.7, 1.9.8, 1.9.9) 45.2.1.8.3 PMD transmit disable 3 (1.9.4) 45.2.1.8.4 PMD transmit disable 2 (1.9.3)
67	45.2.1.8.5 PMD transmit disable 1 (1.9.2) 45.2.1.8.6 PMD transmit disable 0 (1.9.1) 45.2.1.8.7 Global PMD transmit disable (1.9.0) 45.2.1.9 PMD receive signal detect register (Register 1.10)
68	45.2.1.9.1 PMD receive signal detect 9 (1.10.10) 45.2.1.9.2 PMD receive signal detect 4, 5, 6, 7, 8 (1.10.5, 1.10.6, 1.10.7, 1.10.8, 1.10.9) 45.2.1.9.3 PMD receive signal detect 3 (1.10.4) 45.2.1.9.4 PMD receive signal detect 2 (1.10.3) 45.2.1.9.5 PMD receive signal detect 1 (1.10.2)
69	45.2.1.9.6 PMD receive signal detect 0 (1.10.1) 45.2.1.9.7 Global PMD receive signal detect (1.10.0) 45.2.1.10 PMA/PMD extended ability register (Register 1.11)
70	45.2.1.10.1 40G/100G extended abilities (1.11.10) 45.2.1.10.2 P2MP ability (1.11.9) 45.2.1.10.3 10BASE-T ability (1.11.8) 45.2.1.10.4 100BASE-TX ability (1.11.7) 45.2.1.10.5 1000BASE-KX ability (1.11.6) 45.2.1.10.6 1000BASE-T ability (1.11.5) 45.2.1.10.7 10GBASE-KR ability (1.11.4)
71	45.2.1.10.8 10GBASE-KX4 ability (1.11.3) 45.2.1.10.9 10GBASE-T ability (1.11.2) 45.2.1.10.10 10GBASE-LRM ability (1.11.1) 45.2.1.10.11 10GBASE-CX4 ability (1.11.0) 45.2.1.11 10G-EPON PMA/PMD ability register (Register 1.12)
72	45.2.1.11.1 10GBASE-PR-D4 ability (1.12.14) 45.2.1.11.2 10GBASE-PR-U4 ability (1.12.13) 45.2.1.11.3 10/1GBASE-PRX-D4 ability (1.12.12) 45.2.1.11.4 10/1GBASE-PRX-U4 ability (1.12.11) 45.2.1.11.5 10/1GBASE-PRX-D1 ability (1.12.10)
73	45.2.1.11.6 10/1GBASE-PRX-D2 ability (1.12.9) 45.2.1.11.7 10/1GBASE-PRX-D3 ability (1.12.8) 45.2.1.11.8 10GBASE-PR-D1 ability (1.12.7) 45.2.1.11.9 10GBASE-PR-D2 ability (1.12.6) 45.2.1.11.10 10GBASE-PR-D3 ability (1.12.5) 45.2.1.11.11 10/1GBASE-PRX-U1 ability (1.12.4) 45.2.1.11.12 10/1GBASE-PRX-U2 ability (1.12.3) 45.2.1.11.13 10/1GBASE-PRX-U3 ability (1.12.2) 45.2.1.11.14 10GBASE-PR-U1 ability (1.12.1)
74	45.2.1.11.15 10GBASE-PR-U3 ability (1.12.0) 45.2.1.12 40G/100G PMA/PMD extended ability register (Register 1.13)
75	45.2.1.12.1 PMA remote loopback ability (1.13.15) 45.2.1.12.2 100GBASE-CR4 ability (1.13.14) 45.2.1.12.3 100GBASE-KR4 ability (1.13.13) 45.2.1.12.4 100GBASE-KP4 ability (1.13.12) 45.2.1.12.5 100GBASE-ER4 ability (1.13.11) 45.2.1.12.6 100GBASE-LR4 ability (1.13.10) 45.2.1.12.7 100GBASE-SR10 ability (1.13.9) 45.2.1.12.8 100GBASE-CR10 ability (1.13.8) 45.2.1.12.9 100GBASE-SR4 ability (1.13.7)
76	45.2.1.12.10 40GBASE-ER4 ability (1.13.5) 45.2.1.12.11 40GBASE-FR ability (1.13.4) 45.2.1.12.12 40GBASE-LR4 ability (1.13.3) 45.2.1.12.13 40GBASE-SR4 ability (1.13.2) 45.2.1.12.14 40GBASE-CR4 ability (1.13.1) 45.2.1.12.15 40GBASE-KR4 ability (1.13.0) 45.2.1.13 PMA/PMD package identifier (Registers 1.14 and 1.15) 45.2.1.14 EEE capability (Register 1.16)
77	45.2.1.14.1 100GBASE-CR4 EEE deep sleep supported (1.16.11) 45.2.1.14.2 100GBASE-KR4 EEE deep sleep supported (1.16.10) 45.2.1.14.3 100GBASE-KP4 EEE deep sleep supported (1.16.9) 45.2.1.14.4 100GBASE-CR10 EEE deep sleep supported (1.16.8) 45.2.1.14.5 40GBASE-CR4 EEE deep sleep supported (1.16.1) 45.2.1.14.6 40GBASE-KR4 EEE deep sleep supported (1.16.0)
78	45.2.1.15 10P/2B PMA/PMD control register (Register 1.30) 45.2.1.15.1 PMA/PMD link control (1.30.15) 45.2.1.15.2 STFU (1.30.14) 45.2.1.15.3 Silence time (1.30.13:8)
79	45.2.1.15.4 Port subtype select (1.30.7) 45.2.1.15.5 Handshake cleardown (1.30.6) 45.2.1.15.6 Ignore incoming handshake (1.30.5) 45.2.1.15.7 PMA/PMD type selection (1.30.4:0) 45.2.1.16 10P/2B PMA/PMD status register (Register 1.31) 45.2.1.16.1 Data rate (1.31.15:5) 45.2.1.16.2 CO supported (1.31.4)
80	45.2.1.16.3 CPE supported (1.31.3) 45.2.1.16.4 PMA/PMD link status (1.31.2:0) 45.2.1.17 Link partner PMA/PMD control register (Register 1.32)
82	45.2.1.17.1 Get link partner parameters (1.32.15) 45.2.1.17.2 Send link partner parameters (1.32.13) 45.2.1.18 Link partner PMA/PMD status register (Register 1.33) 45.2.1.18.1 Get link partner result (1.33.14)
83	45.2.1.18.2 Send link partner result (1.33.12) 45.2.1.19 10P/2B PMA/PMD link loss register (Register 1.36) 45.2.1.20 10P/2B RX SNR margin register (Register 1.37) 45.2.1.21 10P/2B link partner RX SNR margin register (Register 1.38)
84	45.2.1.22 10P/2B line attenuation register (Register 1.39) 45.2.1.23 10P/2B link partner line attenuation register (Register 1.40) 45.2.1.24 10P/2B line quality thresholds register (Register 1.41) 45.2.1.24.1 Loop attenuation threshold (1.41.15:8)
85	45.2.1.24.2 SNR margin threshold (1.41.7:4) 45.2.1.25 2B link partner line quality thresholds register (Register 1.42) 45.2.1.26 10P FEC correctable errors counter (Register 1.43) 45.2.1.27 10P FEC uncorrectable errors counter (Register 1.44) 45.2.1.28 10P link partner FEC correctable errors register (Register 1.45)
86	45.2.1.29 10P link partner FEC uncorrectable errors register (Register 1.46) 45.2.1.30 10P electrical length register (Register 1.47) 45.2.1.30.1 Electrical length (1.47.15:0) 45.2.1.31 10P link partner electrical length register (Register 1.48) 45.2.1.32 10P PMA/PMD general configuration register (Register 1.49)
87	45.2.1.32.1 TX window length (1.49.7:0) 45.2.1.33 10P PSD configuration register (Register 1.50) 45.2.1.33.1 PBO disable (1.50.8) 45.2.1.34 10P downstream data rate configuration (Registers 1.51, 1.52)
88	45.2.1.35 10P downstream Reed-Solomon configuration (Register 1.53) 45.2.1.35.1 RS codeword length (1.53.0) 45.2.1.36 10P upstream data rate configuration (Registers 1.54, 1.55) 45.2.1.37 10P upstream 10P upstream Reed-Solomon configuration register (Register 1.56)
89	45.2.1.37.1 RS codeword length (1.56.0) 45.2.1.38 10P tone group registers (Registers 1.57, 1.58)
90	45.2.1.39 10P tone control parameters (Registers 1.59, 1.60, 1.61, 1.62, 1.63) 45.2.1.39.1 Tone active (1.59.15) 45.2.1.39.2 Tone direction (1.59.14)
91	45.2.1.39.3 Max SNR margin (1.59.13:5) 45.2.1.39.4 Target SNR margin (1.60.8:0) 45.2.1.39.5 Minimum SNR margin (1.61.8:0) 45.2.1.39.6 PSD level (1.62.8:0) 45.2.1.39.7 USPBO reference (1.63.8:0) 45.2.1.40 10P tone control action register (Register 1.64)
92	45.2.1.40.1 Refresh tone status (1.64.5) 45.2.1.40.2 Change tone activity (1.64.4) 45.2.1.40.3 Change tone direction (1.64.3) 45.2.1.40.4 Change SNR margin (1.64.2)
93	45.2.1.40.5 Change PSD level (1.64.1) 45.2.1.40.6 Change USPBO reference PSD (1.64.0) 45.2.1.41 10P tone status registers (Registers 1.65, 1.66, 1.67)
94	45.2.1.41.1 Refresh status (1.65.15) 45.2.1.41.2 Active (1.65.14) 45.2.1.41.3 Direction (1.65.13) 45.2.1.41.4 RX PSD (1.65.7:0) 45.2.1.41.5 TX PSD (1.66.15:8) 45.2.1.41.6 Bit load (1.66.7:3) 45.2.1.41.7 SNR margin (1.67.9:0) 45.2.1.42 10P outgoing indicator bits status register (Register 1.68)
95	45.2.1.42.1 LoM (1.68.8) 45.2.1.42.2 lpr (1.68.7) 45.2.1.42.3 po (1.68.6) 45.2.1.42.4 Rdi (1.68.5) 45.2.1.42.5 los (1.68.4) 45.2.1.42.6 fec-s (1.68.1)
96	45.2.1.42.7 be-s (1.68.0) 45.2.1.43 10P incoming indicator bits status register (Register 1.69) 45.2.1.43.1 LoM (1.69.8) 45.2.1.43.2 Flpr (1.69.7)
97	45.2.1.43.3 Fpo (1.69.6) 45.2.1.43.4 Rdi (1.69.5) 45.2.1.43.5 Flos (1.69.4) 45.2.1.43.6 Ffec-s (1.69.1) 45.2.1.43.7 Febe-s (1.69.0) 45.2.1.44 10P cyclic extension configuration register (Register 1.70) 45.2.1.45 10P attainable downstream data rate register (Register 1.71)
98	45.2.1.46 2B general parameter register (Register 1.80) 45.2.1.46.1 PMMS target margin (1.80.14:10)
99	45.2.1.46.2 Line probing control (1.80.9) 45.2.1.46.3 Noise environment (1.80.8) 45.2.1.46.4 Region (1.80.1:0) 45.2.1.47 2B PMD parameters registers (Registers 1.81 through 1.88)
101	45.2.1.47.1 Minimum data rate (1.81, 1.83, 1.85, 1.87. Bits 14:8) 45.2.1.47.2 Max data rate (1.81, 1.83, 1.85, 1.87. Bits 6:0)
102	45.2.1.47.3 Data rate step (1.82, 1.84, 1.86, 1.88. Bits 13:7) 45.2.1.47.4 Power (1.82, 1.84, 1.86, 1.88. Bits 6:2) 45.2.1.47.5 Constellation (1.82, 1.84, 1.86, 1.88. Bits 1:0) 45.2.1.48 2B code violation errors counter (Register 1.89) 45.2.1.49 2B link partner code violations register (Register 1.90)
103	45.2.1.50 2B errored seconds counter (Register 1.91) 45.2.1.51 2B link partner errored seconds register (Register 1.92) 45.2.1.52 2B severely errored seconds counter (Register 1.93) 45.2.1.53 2B link partner severely errored seconds register (Register 1.94)
104	45.2.1.54 2B LOSW counter (Register 1.95) 45.2.1.55 2B link partner LOSW register (Register 1.96) 45.2.1.56 2B unavailable seconds counter (Register 1.97)
105	45.2.1.57 2B link partner unavailable seconds register (Register 1.98) 45.2.1.58 2B state defects register (Register 1.99) 45.2.1.58.1 Segment defect (1.99.15) 45.2.1.58.2 SNR margin defect (1.99.14) 45.2.1.58.3 Loop attenuation defect (1.99.13)
106	45.2.1.58.4 Loss of sync word (1.99.12) 45.2.1.59 2B link partner state defects register (Register 1.100) 45.2.1.60 2B negotiated constellation register (Register 1.101) 45.2.1.60.1 Negotiated constellation (1.101.1:0) 45.2.1.61 2B extended PMD parameters registers (Registers 1.102 through 1.109)
108	45.2.1.61.1 Minimum data rate (1.102, 1.104, 1.106, 1.108. Bits 14:8) 45.2.1.61.2 Max data rate (1.102, 1.104, 1.106, 1.108. Bits 6:0)
109	45.2.1.61.3 Data rate step (1.103, 1.105, 1.107, 1.109. Bits 13:7) 45.2.1.61.4 Power (1.103, 1.105, 1.107, 1.109. Bits 6:2) 45.2.1.61.5 Constellation (1.103, 1.105, 1.107, 1.109. Bits 1:0) 45.2.1.62 10GBASE-T status (Register 1.129) 45.2.1.62.1 LP information valid (1.129.0) 45.2.1.63 10GBASE-T pair swap and polarity register (Register 1.130)
110	45.2.1.63.1 Pair D polarity (1.130.11) 45.2.1.63.2 Pair C polarity (1.130.10) 45.2.1.63.3 Pair B polarity (1.130.9) 45.2.1.63.4 Pair A polarity (1.130.8) 45.2.1.63.5 MDI/MDI-X connection (1.130.1:0) 45.2.1.64 10GBASE-T TX power backoff and PHY short reach setting (Register 1.131)
111	45.2.1.64.1 10GBASE-T TX power backoff settings (1.131.15:10) 45.2.1.64.2 PHY short reach mode (1.131.0) 45.2.1.65 10GBASE-T test mode register (Register 1.132) 45.2.1.65.1 Test mode control (1.132.15:13)
112	45.2.1.65.2 Transmitter test frequencies (1.132.12:10) 45.2.1.66 SNR operating margin channel A register (Register 1.133) 45.2.1.67 SNR operating margin channel B register (Register 1.134) 45.2.1.68 SNR operating margin channel C register (Register 1.135)
113	45.2.1.69 SNR operating margin channel D register (Register 1.136) 45.2.1.70 Minimum margin channel A register (Register 1.137) 45.2.1.71 Minimum margin channel B register (Register 1.138) 45.2.1.72 Minimum margin channel C register (Register 1.139) 45.2.1.73 Minimum margin channel D register (Register 1.140) 45.2.1.74 RX signal power channel A register (Register 1.141) 45.2.1.75 RX signal power channel B register (Register 1.142)
114	45.2.1.76 RX signal power channel C register (Register 1.143) 45.2.1.77 RX signal power channel D register (Register 1.144) 45.2.1.78 10GBASE-T skew delay register (Registers 1.145 and 1.146)
115	45.2.1.79 10GBASE-T fast retrain status and control register (Register 1.147) 45.2.1.79.1 LP fast retrain count (1.147.15:11) 45.2.1.79.2 LD fast retrain count (1.147.10:6) 45.2.1.79.3 Fast retrain ability (1.147.4) 45.2.1.79.4 Fast retrain negotiated (1.147.3) 45.2.1.79.5 Fast retrain signal type (1.147.2:1)
116	45.2.1.79.6 Fast retrain enable (1.147.0) 45.2.1.80 BASE-R PMD control register (Register 1.150) 45.2.1.80.1 Restart training (1.150.0) 45.2.1.80.2 Training enable (1.150.1)
117	45.2.1.81 BASE-R PMD status register (Register 1.151)
118	45.2.1.81.1 Receiver status 0 (1.151.0) 45.2.1.81.2 Frame lock 0 (1.151.1) 45.2.1.81.3 Start-up protocol status 0 (1.151.2) 45.2.1.81.4 Training failure 0 (1.151.3) 45.2.1.81.5 Receiver status 1, 2, 3 (1.151.4, 1.151.8, 1.151.12) 45.2.1.81.6 Frame lock 1, 2, 3 (1.151.5, 1.151.9, 1.151.13) 45.2.1.81.7 Start-up protocol status 1, 2, 3 (1.151.6, 1.151.10, 1.151.14) 45.2.1.81.8 Training failure 1, 2, 3 (1.151.7, 1.151.11, 1.151.15) 45.2.1.82 BASE-R LP coefficient update, lane 0 register (Register 1.152) 45.2.1.82.1 Preset (1.152.13)
119	45.2.1.82.2 Initialize (1.152.12) 45.2.1.82.3 Coefficient (k) update (1.152.5:0) 45.2.1.83 BASE-R LP status report, lane 0 register (Register 1.153)
120	45.2.1.83.1 Receiver ready (1.153.15) 45.2.1.83.2 Coefficient (k) status (1.153.5:0) 45.2.1.84 BASE-R LD coefficient update, lane 0 register (Register 1.154)
121	45.2.1.84.1 Preset (1.154.13) 45.2.1.84.2 Initialize (1.154.12) 45.2.1.84.3 Coefficient (k) update(1.154.5:0) 45.2.1.85 BASE-R LD status report, lane 0 register (Register 1.155)
122	45.2.1.85.1 Receiver ready (1.155.15) 45.2.1.85.2 Coefficient (k) status (1.155.5:0) 45.2.1.86 BASE-R PMD status 2 register (Register 1.156)
123	45.2.1.86.1 Receiver status 4, 5, 6, 7 (1.156.0, 1.156.4, 1.156.8, 1.156.12) 45.2.1.86.2 Frame lock 4, 5, 6, 7 (1.156.1, 1.156.5, 1.156.9, 1.156.13) 45.2.1.86.3 Start-up protocol status 4, 5, 6, 7 (1.156.2, 1.156.6, 1.156.10, 1.156.14) 45.2.1.86.4 Training failure 4, 5, 6, 7 (1.156.3, 1.156.7, 1.156.11, 1.156.15)
124	45.2.1.87 BASE-R PMD status 3 register (Register 1.157) 45.2.1.87.1 Receiver status 8, 9 (1.157.0, 1.157.4) 45.2.1.87.2 Frame lock 8, 9 (1.157.1, 1.157.5) 45.2.1.87.3 Start-up protocol status 8, 9 (1.157.2, 1.157.6) 45.2.1.87.4 Training failure 8, 9 (1.157.3, 1.157.7)
125	45.2.1.88 1000BASE-KX control register (Register 1.160) 45.2.1.88.1 PMD transmit disable (1.160.0) 45.2.1.89 1000BASE-KX status register (Register 1.161)
126	45.2.1.89.1 PMD transmit fault ability (1.161.13) 45.2.1.89.2 PMD receive fault ability (1.161.12) 45.2.1.89.3 PMD transmit fault (1.161.11) 45.2.1.89.4 PMD receive fault (1.161.10) 45.2.1.89.5 PMD transmit disable ability (1.161.8) 45.2.1.89.6 1000BASE-KX signal detect (1.161.0)
127	45.2.1.90 PMA overhead control 1, 2, and 3 registers (Register 1.162 through 1.164) 45.2.1.91 PMA overhead status 1 and 2 registers (Register 1.165, 1.166)
128	45.2.1.92 BASE-R FEC ability register (Register 1.170) 45.2.1.92.1 BASE-R FEC ability (1.170.0) 45.2.1.92.2 BASE-R FEC error indication ability (1.170.1) 45.2.1.93 BASE-R FEC control register (Register 1.171) 45.2.1.93.1 FEC enable (1.171.0)
129	45.2.1.93.2 FEC enable error indication (1.171.1) 45.2.1.94 10GBASE-R FEC corrected blocks counter (Register 1.172, 1.173) 45.2.1.95 10GBASE-R FEC uncorrected blocks counter (Register 1.174, 1.175)
130	45.2.1.96 CAUI-4 chip-to-module recommended CTLE register (Register 1.179) 45.2.1.96.1 Recommended CTLE peaking (1.179.4:1) 45.2.1.97 CAUI-4 chip-to-chip transmitter equalization, receive direction, lane 0 register (Register 1.180) 45.2.1.97.1 Request flag (1.180.15)
131	45.2.1.97.2 Post-cursor request (1.180.14:12)
132	45.2.1.97.3 Pre-cursor request (1.180.11:10) 45.2.1.97.4 Post-cursor remote setting (1.180.9:7) 45.2.1.97.5 Pre-cursor remote setting (1.180.6:5) 45.2.1.97.6 Post-cursor local setting (1.180.4:2) 45.2.1.97.7 Pre-cursor local setting (1.180.1:0) 45.2.1.98 CAUI-4 chip-to-chip transmitter equalization, receive direction, lane 1 through lane 3 registers (Registers 1.181, 1.182, 1.183)
133	45.2.1.99 CAUI-4 chip-to-chip transmitter equalization, transmit direction, lane 0 register (Register 1.184)
134	45.2.1.99.1 Request flag (1.184.15) 45.2.1.99.2 Post-cursor request (1.184.14:12) 45.2.1.99.3 Pre-cursor request (1.184.11:10) 45.2.1.99.4 Post-cursor remote setting (1.184.9:7) 45.2.1.99.5 Pre-cursor remote setting (1.184.6:5) 45.2.1.99.6 Post-cursor local setting (1.184.4:2) 45.2.1.99.7 Pre-cursor local setting (1.184.1:0)
135	45.2.1.100 CAUI-4 chip-to-chip transmitter equalization, transmit direction, lane 1 through lane 3 registers (Registers 1.185, 1.186, 1.187) 45.2.1.101 RS-FEC control register (Register 1.200) 45.2.1.101.1 FEC bypass indication enable (1.200.1) 45.2.1.101.2 FEC bypass correction enable (1.200.0) 45.2.1.102 RS-FEC status register (Register 1.201) 45.2.1.102.1 PCS align status (1.201.15)
136	45.2.1.102.2 RS-FEC align status (1.201.14) 45.2.1.102.3 FEC AM lock 3 (1.201.11) 45.2.1.102.4 FEC AM lock 2 (1.201.10)
137	45.2.1.102.5 FEC AM lock 1 (1.201.9) 45.2.1.102.6 FEC AM lock 0 (1.201.8) 45.2.1.102.7 RS-FEC high SER (1.201.2) 45.2.1.102.8 FEC bypass indication ability (1.201.1) 45.2.1.102.9 FEC bypass correction ability (1.201.0) 45.2.1.103 RS-FEC corrected codewords counter (Register 1.202, 1.203)
138	45.2.1.104 RS-FEC uncorrected codewords counter (Register 1.204, 1.205) 45.2.1.105 RS-FEC lane mapping register (Register 1.206) 45.2.1.106 RS-FEC symbol error counter lane 0 (Register 1.210, 1.211)
139	45.2.1.107 RS-FEC symbol error counter lane 1 through 3 (Register 1.212, 1.213, 1.214, 1.215, 1.216, 1.217) 45.2.1.108 RS-FEC BIP error counter lane 0 (Register 1.230) 45.2.1.109 RS-FEC BIP error counter, lane 1 through 19 (Registers 1.231 through 1.249) 45.2.1.110 RS-FEC PCS lane 0 mapping register (Register 1.250)
140	45.2.1.111 RS-FEC PCS lanes 1 through 19 mapping registers (Registers 1.251 through 1.269) 45.2.1.112 RS-FEC PCS alignment status 1 register (Register 1.280)
141	45.2.1.112.1 Block 7 lock (1.280.7) 45.2.1.112.2 Block 6 lock (1.280.6) 45.2.1.112.3 Block 5 lock (1.280.5) 45.2.1.112.4 Block 4 lock (1.280.4) 45.2.1.112.5 Block 3 lock (1.280.3) 45.2.1.112.6 Block 2 lock (1.280.2)
142	45.2.1.112.7 Block 1 lock (1.280.1) 45.2.1.112.8 Block 0 lock (1.280.0) 45.2.1.113 RS-FEC PCS alignment status 2 register (Register 1.281)
143	45.2.1.113.1 Block 19 lock (1.281.11) 45.2.1.113.2 Block 18 lock (1.281.10) 45.2.1.113.3 Block 17 lock (1.281.9) 45.2.1.113.4 Block 16 lock (1.281.8) 45.2.1.113.5 Block 15 lock (1.281.7) 45.2.1.113.6 Block 14 lock (1.281.6)
144	45.2.1.113.7 Block 13 lock (1.281.5) 45.2.1.113.8 Block 12 lock (1.281.4) 45.2.1.113.9 Block 11 lock (1.281.3) 45.2.1.113.10 Block 10 lock (1.281.2) 45.2.1.113.11 Block 9 lock (1.281.1) 45.2.1.113.12 Block 8 lock (1.281.0) 45.2.1.114 RS-FEC PCS alignment status 3 register (Register 1.282) 45.2.1.114.1 Lane 7 aligned (1.282.7)
145	45.2.1.114.2 Lane 6 aligned (1.282.6) 45.2.1.114.3 Lane 5 aligned (1.282.5) 45.2.1.114.4 Lane 4 aligned (1.282.4) 45.2.1.114.5 Lane 3 aligned (1.282.3)
146	45.2.1.114.6 Lane 2 aligned (1.282.2) 45.2.1.114.7 Lane 1 aligned (1.282.1) 45.2.1.114.8 Lane 0 aligned (1.282.0) 45.2.1.115 RS-FEC PCS alignment status 4 register (Register 1.283)
147	45.2.1.115.1 Lane 19 aligned (1.283.11) 45.2.1.115.2 Lane 18 aligned (1.283.10) 45.2.1.115.3 Lane 17 aligned (1.283.9) 45.2.1.115.4 Lane 16 aligned (1.283.8) 45.2.1.115.5 Lane 15 aligned (1.283.7)
148	45.2.1.115.6 Lane 14 aligned (1.283.6) 45.2.1.115.7 Lane 13 aligned (1.283.5) 45.2.1.115.8 Lane 12 aligned (1.283.4) 45.2.1.115.9 Lane 11 aligned (1.283.3) 45.2.1.115.10 Lane 10 aligned (1.283.2) 45.2.1.115.11 Lane 9 aligned (1.283.1) 45.2.1.115.12 Lane 8 aligned (1.283.0) 45.2.1.116 BASE-R FEC corrected blocks counter, lanes 0 through 19
149	45.2.1.117 BASE-R FEC uncorrected blocks counter, lanes 0 through 19 45.2.1.118 BASE-R LP coefficient update register, lanes 1 through 9 45.2.1.119 BASE-R LP status report register, lanes 1 through 9 45.2.1.120 BASE-R LD coefficient update register, lanes 1 through 9 45.2.1.121 BASE-R LD status report register, lanes 1 through 9
150	45.2.1.122 PMD training pattern lanes 0 through 3 (Register 1.1450 through 1.1453) 45.2.1.123 Test-pattern ability (Register 1.1500)
151	45.2.1.124 PRBS pattern testing control (Register 1.1501)
152	45.2.1.125 Square wave testing control (Register 1.1510)
153	45.2.1.126 PRBS Tx pattern testing error counter (Register 1.1600, 1.1601, 1.1602, 1.1603, 1.1604, 1.1605, 1.1606, 1.1607, 1.1608, 1.1609)
154	45.2.1.127 PRBS Rx pattern testing error counter (Register 1.1700, 1.1701, 1.1702, 1.1703, 1.1704, 1.1705, 1.1706, 1.1707, 1.1708, 1.1709) 45.2.1.128 TimeSync PMA/PMD capability (Register 1.1800) 45.2.1.129 TimeSync PMA/PMD transmit path data delay (Registers 1.1801, 1.1802, 1.1803, 1.1804)
155	45.2.1.130 TimeSync PMA/PMD receive path data delay (Registers 1.1805, 1.1806, 1.1807, 1.1808) 45.2.2 WIS registers
157	45.2.2.1 WIS control 1 register (Register 2.0) 45.2.2.1.1 Reset (2.0.15)
158	45.2.2.1.2 Loopback (2.0.14) 45.2.2.1.3 Low power (2.0.11) 45.2.2.1.4 Speed selection (2.0.13, 2.0.6, and 2.0.5:2) 45.2.2.2 WIS status 1 register (Register 2.1)
159	45.2.2.2.1 Fault (2.1.7) 45.2.2.2.2 Link status (2.1.2) 45.2.2.2.3 Low-power ability (2.1.1) 45.2.2.3 WIS device identifier (Registers 2.2 and 2.3) 45.2.2.4 WIS speed ability (Register 2.4)
160	45.2.2.4.1 10G capable (2.4.0) 45.2.2.5 WIS devices in package (Registers 2.5 and 2.6) 45.2.2.6 10G WIS control 2 register (Register 2.7)
161	45.2.2.6.1 PRBS31 receive test-pattern enable (2.7.5) 45.2.2.6.2 PRBS31 transmit test-pattern enable (2.7.4) 45.2.2.6.3 Test-pattern selection (2.7.3) 45.2.2.6.4 Receive test-pattern enable (2.7.2) 45.2.2.6.5 Transmit test-pattern enable (2.7.1) 45.2.2.6.6 PCS type selection (2.7.0) 45.2.2.7 10G WIS status 2 register (Register 2.8) 45.2.2.7.1 Device present (2.8.15:14)
162	45.2.2.7.2 PRBS31 pattern testing ability (2.8.1) 45.2.2.7.3 10GBASE-R ability (2.8.0) 45.2.2.8 10G WIS test-pattern error counter register (Register 2.9)
163	45.2.2.9 WIS package identifier (Registers 2.14 and 2.15) 45.2.2.10 10G WIS status 3 register (Register 2.33)
164	45.2.2.10.1 SEF (2.33.11) 45.2.2.10.2 Far end PLM-P/LCD-P (2.33.10) 45.2.2.10.3 Far end AIS-P/LOP-P (2.33.9) 45.2.2.10.4 LOF (2.33.7)
165	45.2.2.10.5 LOS (2.33.6) 45.2.2.10.6 RDI-L (2.33.5) 45.2.2.10.7 AIS-L (2.33.4) 45.2.2.10.8 LCD-P (2.33.3) 45.2.2.10.9 PLM-P (2.33.2) 45.2.2.10.10 AIS-P (2.33.1) 45.2.2.10.11 LOP-P (2.33.0)
166	45.2.2.11 10G WIS far end path block error count (Register 2.37) 45.2.2.12 10G WIS J1 transmit (Registers 2.39 through 2.46)
167	45.2.2.13 10G WIS J1 receive (Registers 2.47 through 2.54)
168	45.2.2.14 10G WIS far end line BIP errors (Registers 2.55 and 2.56) 45.2.2.15 10G WIS line BIP errors (Registers 2.57 and 2.58)
169	45.2.2.16 10G WIS path block error count (Register 2.59) 45.2.2.16.1 Path block error count (2.59.15:0) 45.2.2.17 10G WIS section BIP error count (Register 2.60) 45.2.2.17.1 Section BIP error count (2.60.15:0)
170	45.2.2.18 10G WIS J0 transmit (Registers 2.64 through 2.71) 45.2.2.19 10G WIS J0 receive (Registers 2.72 through 2.79)
172	45.2.2.20 TimeSync WIS capability (Register 2.1800) 45.2.2.21 TimeSync WIS transmit path data delay (Registers 2.1801, 2.1802, 2.1803, 2.1804) 45.2.2.22 TimeSync WIS receive path data delay (Registers 2.1805, 2.1806, 2.1807, 2.1808)
173	45.2.3 PCS registers
175	45.2.3.1 PCS control 1 register (Register 3.0) 45.2.3.1.1 Reset (3.0.15)
176	45.2.3.1.2 Loopback (3.0.14) 45.2.3.1.3 Low power (3.0.11) 45.2.3.1.4 Clock stop enable (3.0.10) 45.2.3.1.5 Speed selection (3.0.13, 3.0.6, 3.0.5:2)
177	45.2.3.2 PCS status 1 register (Register 3.1) 45.2.3.2.1 Transmit LPI received (3.1.11) 45.2.3.2.2 Receive LPI received (3.1.10)
178	45.2.3.2.3 Transmit LPI indication (3.1.9) 45.2.3.2.4 Receive LPI indication (3.1.8) 45.2.3.2.5 Fault (3.1.7) 45.2.3.2.6 Clock stop capable (3.1.6) 45.2.3.2.7 PCS receive link status (3.1.2) 45.2.3.2.8 Low-power ability (3.1.1) 45.2.3.3 PCS device identifier (Registers 3.2 and 3.3) 45.2.3.4 PCS speed ability (Register 3.4)
179	45.2.3.4.1 10G capable (3.4.0) 45.2.3.4.2 10PASS-TS/2BASE-TL capable 45.2.3.4.3 40G capable (3.4.2) 45.2.3.4.4 100G capable (3.4.3) 45.2.3.5 PCS devices in package (Registers 3.5 and 3.6) 45.2.3.6 PCS control 2 register (Register 3.7) 45.2.3.6.1 PCS type selection (3.7.2:0)
180	45.2.3.7 PCS status 2 register (Register 3.8)
181	45.2.3.7.1 Device present (3.8.15:14) 45.2.3.7.2 Transmit fault (3.8.11) 45.2.3.7.3 Receive fault (3.8.10) 45.2.3.7.4 100GBASE-R capable (3.8.5) 45.2.3.7.5 40GBASE-R capable (3.8.4) 45.2.3.7.6 10GBASE-T capable (3.8.3)
182	45.2.3.7.7 10GBASE-W capable (3.8.2) 45.2.3.7.8 10GBASE-X capable (3.8.1) 45.2.3.7.9 10GBASE-R capable (3.8.0) 45.2.3.8 PCS package identifier (Registers 3.14 and 3.15) 45.2.3.9 EEE control and capability (Register 3.20)
183	45.2.3.9.1 100GBASE-R EEE deep sleep supported (3.20.13) 45.2.3.9.2 100GBASE-R EEE fast wake supported (3.20.12) 45.2.3.9.3 40GBASE-R EEE deep sleep supported (3.20.9) 45.2.3.9.4 40GBASE-R EEE fast wake supported (3.20.8) 45.2.3.9.5 10GBASE-KR EEE supported (3.20.6) 45.2.3.9.6 10GBASE-KX4 EEE supported (3.20.5)
184	45.2.3.9.7 1000BASE-KX EEE supported (3.20.4) 45.2.3.9.8 10GBASE-T EEE supported (3.20.3) 45.2.3.9.9 1000BASE-T EEE supported (3.20.2) 45.2.3.9.10 100BASE-TX EEE supported (3.20.1) 45.2.3.9.11 LPI_FW (3.20.0) 45.2.3.10 EEE wake error counter (Register 3.22) 45.2.3.11 10GBASE-X PCS status register (Register 3.24)
185	45.2.3.11.1 10GBASE-X receive lane alignment status (3.24.12) 45.2.3.11.2 Pattern testing ability (3.24.11) 45.2.3.11.3 Lane 3 sync (3.24.3) 45.2.3.11.4 Lane 2 sync (3.24.2) 45.2.3.11.5 Lane 1 sync (3.24.1) 45.2.3.11.6 Lane 0 sync (3.24.0)
186	45.2.3.12 10GBASE-X PCS test control register (Register 3.25) 45.2.3.12.1 Transmit test-pattern enable (3.25.2) 45.2.3.12.2 Test pattern select (3.25.1:0) 45.2.3.13 BASE-R and 10GBASE-T PCS status 1 register (Register 3.32)
187	45.2.3.13.1 BASE-R and 10GBASE-T receive link status (3.32.12) 45.2.3.13.2 PRBS9 pattern testing ability (3.32.3) 45.2.3.13.3 PRBS31 pattern testing ability (3.32.2) 45.2.3.13.4 BASE-R and 10GBASE-T PCS high BER (3.32.1)
188	45.2.3.13.5 BASE-R and 10GBASE-T PCS block lock (3.32.0) 45.2.3.14 BASE-R and 10GBASE-T PCS status 2 register (Register 3.33) 45.2.3.14.1 Latched block lock (3.33.15)
189	45.2.3.14.2 Latched high BER (3.33.14) 45.2.3.14.3 BER (3.33.13:8) 45.2.3.14.4 Errored blocks (3.33.7:0) 45.2.3.15 10GBASE-R PCS test pattern seed A (Registers 3.34 through 3.37)
190	45.2.3.16 10GBASE-R PCS test pattern seed B (Registers 3.38 through 3.41) 45.2.3.17 BASE-R PCS test-pattern control register (Register 3.42)
191	45.2.3.17.1 Scrambled idle test-pattern enable (3.42.7) 45.2.3.17.2 10GBASE-R PRBS9 transmit test-pattern enable (3.42.6) 45.2.3.17.3 10GBASE-R PRBS31 receive test-pattern enable (3.42.5) 45.2.3.17.4 10GBASE-R PRBS31 transmit test-pattern enable (3.42.4)
192	45.2.3.17.5 Transmit test-pattern enable (3.42.3) 45.2.3.17.6 Receive test-pattern enable (3.42.2) 45.2.3.17.7 Test-pattern select (3.42.1) 45.2.3.17.8 Data pattern select (3.42.0) 45.2.3.18 BASE-R PCS test-pattern error counter register (Register 3.43)
193	45.2.3.19 BER high order counter (Register 3.44) 45.2.3.20 Errored blocks high order counter (Register 3.45) 45.2.3.21 Multi-lane BASE-R PCS alignment status 1 register (Register 3.50)
194	45.2.3.21.1 Multi-lane BASE-R PCS alignment status (3.50.12) 45.2.3.21.2 Block 7 lock (3.50.7)
195	45.2.3.21.3 Block 6 lock (3.50.6) 45.2.3.21.4 Block 5 lock (3.50.5) 45.2.3.21.5 Block 4 lock (3.50.4) 45.2.3.21.6 Block 3 lock (3.50.3) 45.2.3.21.7 Block 2 lock (3.50.2) 45.2.3.21.8 Block 1 lock (3.50.1) 45.2.3.21.9 Block 0 lock (3.50.0) 45.2.3.22 Multi-lane BASE-R PCS alignment status 2 register (Register 3.51)
196	45.2.3.22.1 Block 19 lock (3.51.11) 45.2.3.22.2 Block 18 lock (3.51.10)
197	45.2.3.22.3 Block 17 lock (3.51.9) 45.2.3.22.4 Block 16 lock (3.51.8) 45.2.3.22.5 Block 15 lock (3.51.7) 45.2.3.22.6 Block 14 lock (3.51.6) 45.2.3.22.7 Block 13 lock (3.51.5) 45.2.3.22.8 Block 12 lock (3.51.4) 45.2.3.22.9 Block 11 lock (3.51.3) 45.2.3.22.10 Block 10 lock (3.51.2) 45.2.3.22.11 Block 9 lock (3.51.1)
198	45.2.3.22.12 Block 8 lock (3.51.0) 45.2.3.23 Multi-lane BASE-R PCS alignment status 3 register (Register 3.52) 45.2.3.23.1 Lane 7 aligned (3.52.7)
199	45.2.3.23.2 Lane 6 aligned (3.52.6) 45.2.3.23.3 Lane 5 aligned (3.52.5) 45.2.3.23.4 Lane 4 aligned (3.52.4) 45.2.3.23.5 Lane 3 aligned (3.52.3) 45.2.3.23.6 Lane 2 aligned (3.52.2) 45.2.3.23.7 Lane 1 aligned (3.52.1) 45.2.3.23.8 Lane 0 aligned (3.52.0) 45.2.3.24 Multi-lane BASE-R PCS alignment status 4 register (Register 3.53)
200	45.2.3.24.1 Lane 19 aligned (3.53.11) 45.2.3.24.2 Lane 18 aligned (3.53.10)
201	45.2.3.24.3 Lane 17 aligned (3.53.9) 45.2.3.24.4 Lane 16 aligned (3.53.8) 45.2.3.24.5 Lane 15 aligned (3.53.7) 45.2.3.24.6 Lane 14 aligned (3.53.6) 45.2.3.24.7 Lane 13 aligned (3.53.5) 45.2.3.24.8 Lane 12 aligned (3.53.4) 45.2.3.24.9 Lane 11 aligned (3.53.3) 45.2.3.24.10 Lane 10 aligned (3.53.2) 45.2.3.24.11 Lane 9 aligned (3.53.1)
202	45.2.3.24.12 Lane 8 aligned (3.53.0) 45.2.3.25 10P/2B capability register (3.60) 45.2.3.25.1 PAF available (3.60.12) 45.2.3.25.2 Remote PAF supported (3.60.11) 45.2.3.26 10P/2B PCS control register (Register 3.61)
203	45.2.3.26.1 MII receive during transmit (3.61.15) 45.2.3.26.2 TX_EN and CRS infer a collision (3.61.14) 45.2.3.26.3 PAF enable (3.61.0) 45.2.3.27 10P/2B PME available (Registers 3.62 and 3.63)
204	45.2.3.28 10P/2B PME aggregate registers (Registers 3.64 and 3.65) 45.2.3.29 10P/2B PAF RX error register (Register 3.66)
205	45.2.3.30 10P/2B PAF small fragments register (Register 3.67) 45.2.3.31 10P/2B PAF large fragments register (Register 3.68)
206	45.2.3.32 10P/2B PAF overflow register (Register 3.69) 45.2.3.33 10P/2B PAF bad fragments register (Register 3.70) 45.2.3.34 10P/2B PAF lost fragments register (Register 3.71)
207	45.2.3.35 10P/2B PAF lost starts of fragments register (Register 3.72) 45.2.3.36 10P/2B PAF lost ends of fragments register (Register 3.73) 45.2.3.37 10GBASE-PR and 10/1GBASE-PRX FEC ability register (Register 3.74)
208	45.2.3.38 10GBASE-PR and 10/1GBASE-PRX FEC control register (Register 3.75) 45.2.3.38.1 FEC enable error indication (3.75.1) 45.2.3.38.2 10 Gb/s FEC Enable (3.75.0) 45.2.3.39 10/1GBASE-PRX and 10GBASE-PR corrected FEC codewords counter (Register 3.76, 3.77)
209	45.2.3.40 10/1GBASE-PRX and 10GBASE-PR uncorrected FEC codewords counter (Register 3.78, 3.79) 45.2.3.41 10GBASE-PR and 10/1GBASE-PRX BER monitor timer control register (Register 3.80)
210	45.2.3.42 10GBASE-PR and 10/1GBASE-PRX BER monitor status (Register 3.81) 45.2.3.42.1 10GBASE-PR and 10/1GBASE-PRX PCS high BER (3.81.0) 45.2.3.42.2 10GBASE-PR and 10/1GBASE-PRX PCS latched high BER (3.81.1) 45.2.3.43 10GBASE-PR and 10/1GBASE-PRX BER monitor threshold control (Register 3.82)
211	45.2.3.44 BIP error counter lane 0 (Register 3.200) 45.2.3.45 BIP error counter, lanes 1 through 19 (Registers 3.201 through 3.219) 45.2.3.46 Lane 0 mapping register (Register 3.400) 45.2.3.47 Lanes 1 through 19 mapping registers (Registers 3.401 through 3.419)
212	45.2.3.48 TimeSync PCS capability (Register 3.1800) 45.2.3.49 TimeSync PCS transmit path data delay (Registers 3.1801, 3.1802, 3.1803, 3.1804) 45.2.3.50 TimeSync PCS receive path data delay (Registers 3.1805, 3.1806, 3.1807, 3.1808)
213	45.2.4 PHY XS registers
214	45.2.4.1 PHY XS control 1 register (Register 4.0)
215	45.2.4.1.1 Reset (4.0.15) 45.2.4.1.2 Loopback (4.0.14) 45.2.4.1.3 Low power (4.0.11) 45.2.4.1.4 Clock stop enable (4.0.10) 45.2.4.1.5 XAUI stop enable (4.0.9)
216	45.2.4.1.6 Speed selection (4.0.13, 4.0.6, 4.0.5:2) 45.2.4.2 PHY XS status 1 register (Register 4.1)
217	45.2.4.2.1 Transmit LPI received (4.1.11) 45.2.4.2.2 Receive LPI received (4.1.10) 45.2.4.2.3 Transmit LPI indication (4.1.9) 45.2.4.2.4 Receive LPI indication (4.1.8) 45.2.4.2.5 Fault (4.1.7) 45.2.4.2.6 Clock stop capable (4.1.6) 45.2.4.2.7 PHY XS transmit link status (4.1.2) 45.2.4.2.8 Low-power ability (4.1.1)
218	45.2.4.3 PHY XS device identifier (Registers 4.2 and 4.3) 45.2.4.4 PHY XS speed ability (Register 4.4) 45.2.4.4.1 10G capable (4.4.0) 45.2.4.5 PHY XS devices in package (Registers 4.5 and 4.6) 45.2.4.6 PHY XS status 2 register (Register 4.8)
219	45.2.4.6.1 Device present (4.8.15:14) 45.2.4.6.2 Transmit fault (4.8.11) 45.2.4.6.3 Receive fault (4.8.10) 45.2.4.7 PHY XS package identifier (Registers 4.14 and 4.15)
220	45.2.4.8 EEE capability (Register 4.20) 45.2.4.8.1 PHY XS EEE supported (4.20.4) 45.2.4.8.2 XAUI stop capable (4.20.0) 45.2.4.9 EEE wake error counter (Register 4.22) 45.2.4.10 10G PHY XGXS lane status register (Register 4.24) 45.2.4.10.1 PHY XGXS transmit lane alignment status (4.24.12)
221	45.2.4.10.2 Pattern testing ability (4.24.11) 45.2.4.10.3 PHY XS loopback ability (4.24.10) 45.2.4.10.4 Lane 3 sync (4.24.3) 45.2.4.10.5 Lane 2 sync (4.24.2)
222	45.2.4.10.6 Lane 1 sync (4.24.1) 45.2.4.10.7 Lane 0 sync (4.24.0) 45.2.4.11 10G PHY XGXS test control register (Register 4.25) 45.2.4.11.1 10G PHY XGXS test-pattern enable (4.25.2) 45.2.4.11.2 10G PHY XGXS test-pattern select (4.25.1:0)
223	45.2.4.12 TimeSync PHY XS capability (Register 4.1800) 45.2.4.13 TimeSync PHY XS transmit path data delay (Registers 4.1801, 4.1802, 4.1803, 4.1804) 45.2.4.14 TimeSync PHY XS receive path data delay (Registers 4.1805, 4.1806, 4.1807, 4.1808)
224	45.2.5 DTE XS registers
225	45.2.5.1 DTE XS control 1 register (Register 5.0)
226	45.2.5.1.1 Reset (5.0.15) 45.2.5.1.2 Loopback (5.0.14) 45.2.5.1.3 Low power (5.0.11) 45.2.5.1.4 Clock stop enable (5.0.10)
227	45.2.5.1.5 XAUI stop enable (5.0.9) 45.2.5.1.6 Speed selection (5.0.13, 5.0.6, 5.0.5:2) 45.2.5.2 DTE XS status 1 register (Register 5.1)
228	45.2.5.2.1 Transmit LPI received (5.1.11) 45.2.5.2.2 Receive LPI received (5.1.10) 45.2.5.2.3 Transmit LPI indication (5.1.9) 45.2.5.2.4 Receive LPI indication (5.1.8) 45.2.5.2.5 Fault (5.1.7) 45.2.5.2.6 Clock stop capable (5.1.6) 45.2.5.2.7 DTE XS receive link status (5.1.2)
229	45.2.5.2.8 Low-power ability (5.1.1) 45.2.5.3 DTE XS device identifier (Registers 5.2 and 5.3) 45.2.5.4 DTE XS speed ability (Register 5.4) 45.2.5.4.1 10G capable (5.4.0) 45.2.5.5 DTE XS devices in package (Registers 5.5 and 5.6) 45.2.5.6 DTE XS status 2 register (Register 5.8) 45.2.5.6.1 Device present (5.8.15:14)
230	45.2.5.6.2 Transmit fault (5.8.11) 45.2.5.6.3 Receive fault (5.8.10) 45.2.5.7 DTE XS package identifier (Registers 5.14 and 5.15)
231	45.2.5.8 EEE capability (Register 5.20) 45.2.5.8.1 PHY XS EEE supported (5.20.4) 45.2.5.8.2 XAUI stop capable (5.20.0) 45.2.5.9 EEE wake error counter (Register 5.22) 45.2.5.10 10G DTE XGXS lane status register (Register 5.24) 45.2.5.10.1 DTE XGXS receive lane alignment status (5.24.12)
232	45.2.5.10.2 Pattern testing ability (5.24.11) 45.2.5.10.3 Ignored (5.24.10) 45.2.5.10.4 Lane 3 sync (5.24.3) 45.2.5.10.5 Lane 2 sync (5.24.2) 45.2.5.10.6 Lane 1 sync (5.24.1)
233	45.2.5.10.7 Lane 0 sync (5.24.0) 45.2.5.11 10G DTE XGXS test control register (Register 5.25) 45.2.5.11.1 10G DTE XGXS test-pattern enable (5.25.2) 45.2.5.11.2 10G DTE XGXS test-pattern select (5.25.1:0) 45.2.5.12 TimeSync DTE XS capability (Register 5.1800)
234	45.2.5.13 TimeSync DTE XS transmit path data delay (Registers 5.1801, 5.1802, 5.1803, 5.1804) 45.2.5.14 TimeSync DTE XS receive path data delay (Registers 5.1805, 5.1806, 5.1807, 5.1808)
235	45.2.6 TC registers
236	45.2.6.1 TC control register (Register 6.0) 45.2.6.1.1 Reset (6.0.15)
237	45.2.6.1.2 Speed selection (6.0.13, 6.0.6, 6.0.5:2) 45.2.6.2 TC device identifier (Registers 6.2 and 6.3) 45.2.6.3 TC speed ability (Register 6.4)
238	45.2.6.3.1 10PASS-TS/2BASE-TL capable (6.4.1) 45.2.6.4 TC devices in package registers (Registers 6.5, 6.6) 45.2.6.5 TC package identifier registers (Registers 6.14, 6.15) 45.2.6.6 10P/2B aggregation discovery control register (Register 6.16) 45.2.6.6.1 Discovery operation (6.16.1:0)
239	45.2.6.7 10P/2B aggregation and discovery status register (Register 6.17) 45.2.6.7.1 Link partner aggregate operation result (6.17.1)
240	45.2.6.7.2 Discovery operation result (6.17.0) 45.2.6.8 10P/2B aggregation discovery code (Registers 6.18, 6.19, 6.20) 45.2.6.9 10P/2B link partner PME aggregate control register (Register 6.21)
241	45.2.6.9.1 Link partner aggregate operation (6.21.1:0) 45.2.6.10 10P/2B link partner PME aggregate data (Registers 6.22, 6.23)
242	45.2.6.11 10P/2B TC CRC error register (Register 6.24) 45.2.6.12 10P/2B TPS-TC coding violations counter (Registers 6.25, 6.26) 45.2.6.13 10P/2B TC indications register (Register 6.27)
243	45.2.6.13.1 Local TC synchronized (6.27.8) 45.2.6.13.2 Remote TC synchronized (6.27.0) 45.2.6.14 TimeSync TC capability (Register 6.1800) 45.2.6.15 TimeSync TC transmit path data delay (Registers 6.1801, 6.1802, 6.1803, 6.1804)
244	45.2.6.16 TimeSync TC receive path data delay (Registers 6.1805, 6.1806, 6.1807, 6.1808) 45.2.7 Auto-Negotiation registers
245	45.2.7.1 AN control register (Register 7.0) 45.2.7.1.1 AN reset (7.0.15)
246	45.2.7.1.2 Extended Next Page control (7.0.13) 45.2.7.1.3 Auto-Negotiation enable (7.0.12) 45.2.7.1.4 Restart Auto-Negotiation (7.0.9) 45.2.7.2 AN status (Register 7.1)
247	45.2.7.2.1 Parallel detection fault (7.1.9) 45.2.7.2.2 Extended Next Page status (7.1.7) 45.2.7.2.3 Page received (7.1.6) 45.2.7.2.4 Auto-Negotiation complete (7.1.5) 45.2.7.2.5 Remote fault (7.1.4)
248	45.2.7.2.6 Auto-Negotiation ability (7.1.3) 45.2.7.2.7 Link status (7.1.2) 45.2.7.2.8 Link partner Auto-Negotiation ability (7.1.0) 45.2.7.3 Auto-Negotiation device identifier (Registers 7.2 and 7.3) 45.2.7.4 AN devices in package (Registers 7.5 and 7.6) 45.2.7.5 AN package identifier (Registers 7.14 and 7.15)
249	45.2.7.6 AN advertisement register (7.16, 7.17, and 7.18)
250	45.2.7.7 AN LP Base Page ability register (7.19, 7.20, and 7.21) 45.2.7.8 AN XNP transmit register (7.22, 7.23, and 7.24)
251	45.2.7.9 AN LP XNP ability register (7.25, 7.26, and 7.27)
252	45.2.7.10 10GBASE-T AN control register (Register 7.32) 45.2.7.10.1 MASTER-SLAVE manual config enable (7.32.15) 45.2.7.10.2 MASTER-SLAVE config value (7.32.14)
253	45.2.7.10.3 Port type (7.32.13) 45.2.7.10.4 10GBASE-T capability (7.32.12) 45.2.7.10.5 LD PMA training reset request (7.32.2) 45.2.7.10.6 Fast retrain ability 45.2.7.10.7 LD loop timing ability (7.32.0)
254	45.2.7.11 10GBASE-T AN status register (Register 7.33) 45.2.7.11.1 MASTER-SLAVE configuration fault (7.33.15) 45.2.7.11.2 MASTER-SLAVE configuration resolution (7.33.14)
255	45.2.7.11.3 Local receiver status (7.33.13) 45.2.7.11.4 Remote receiver status (7.33.12) 45.2.7.11.5 Link partner 10GBASE-T capability (7.33.11) 45.2.7.11.6 Link partner loop timing ability (7.33.10) 45.2.7.11.7 Link partner PMA training reset request (7.33.9) 45.2.7.11.8 Fast retrain ability (7.33.1) 45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48)
256	45.2.7.12.1 BASE-R FEC negotiated (7.48.4) 45.2.7.12.2 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8, 7.48.9, 7.48.10, 7.48.11) 45.2.7.12.3 Backplane Ethernet, BASE-R copper AN ability (7.48.0)
257	45.2.7.13 EEE advertisement (Register 7.60)
258	45.2.7.13.1 100GBASE-CR4 EEE supported (7.60.13) 45.2.7.13.2 100GBASE-KR4 EEE supported (7.60.12) 45.2.7.13.3 100GBASE-KP4 EEE supported (7.60.11) 45.2.7.13.4 100GBASE-CR10 EEE supported (7.60.10)
259	45.2.7.13.5 40GBASE-CR4 EEE supported (7.60.8) 45.2.7.13.6 40GBASE-KR4 EEE supported (7.60.7) 45.2.7.13.7 10GBASE-KR EEE supported (7.60.6) 45.2.7.13.8 10GBASE-KX4 EEE supported (7.60.5) 45.2.7.13.9 1000BASE-KX EEE supported (7.60.4) 45.2.7.13.10 10GBASE-T EEE supported (7.60.3) 45.2.7.13.11 1000BASE-T EEE supported (7.60.2) 45.2.7.13.12 100BASE-TX EEE supported (7.60.1) 45.2.7.14 EEE link partner ability (Register 7.61)
261	45.2.8 Clause 22 extension registers
262	45.2.8.1 Clause 22 extension devices in package registers (Registers 29.5, 29.6) 45.2.8.2 FEC capability register (Register 29.7) 45.2.8.2.1 FEC capable (29.7.0) 45.2.8.3 FEC control register (Register 29.8) 45.2.8.3.1 FEC enable (29.8.0) 45.2.8.4 FEC buffer head coding violation counter (Register 29.9)
263	45.2.8.5 FEC corrected blocks counter (Register 29.10) 45.2.8.6 FEC uncorrected blocks counter (Register 29.11) 45.2.9 Vendor specific MMD 1 registers
264	45.2.9.1 Vendor specific MMD 1 device identifier (Registers 30.2 and 30.3) 45.2.9.2 Vendor specific MMD 1 status register (Register 30.8) 45.2.9.2.1 Device present (30.8.15:14)
265	45.2.9.3 Vendor specific MMD 1 package identifier (Registers 30.14 and 30.15) 45.2.10 Vendor specific MMD 2 registers 45.2.10.1 Vendor specific MMD 2 device identifier (Registers 31.2 and 31.3) 45.2.10.2 Vendor specific MMD 2 status register (Register 31.8)
266	45.2.10.2.1 Device present (31.8.15:14) 45.2.10.3 Vendor specific MMD 2 package identifier (Registers 31.14 and 31.15) 45.3 Management frame structure
267	45.3.1 IDLE (idle condition) 45.3.2 PRE (preamble) 45.3.3 ST (start of frame) 45.3.4 OP (operation code)
268	45.3.5 PRTAD (port address) 45.3.6 DEVAD (device address) 45.3.7 TA (turnaround) 45.3.8 ADDRESS / DATA 45.4 Electrical interface 45.4.1 Electrical specification
269	45.4.2 Timing specification
271	45.5 Protocol implementation conformance statement (PICS) proforma for Clause 45, Management Data Input/Output (MDIO) interface 45.5.1 Introduction 45.5.2 Identification 45.5.2.1 Implementation identification 45.5.2.2 Protocol summary
272	45.5.2.3 Major capabilities/options 45.5.3 PICS proforma tables for the Management Data Input Output (MDIO) interface 45.5.3.1 MDIO signal functional specifications 45.5.3.2 PMA/PMD MMD options
274	45.5.3.3 PMA/PMD management functions
281	45.5.3.4 WIS options 45.5.3.5 WIS management functions
284	45.5.3.6 PCS options
285	45.5.3.7 PCS management functions
291	45.5.3.8 Auto-Negotiation options 45.5.3.9 Auto-Negotiation management functions
295	45.5.3.10 PHY XS options 45.5.3.11 PHY XS management functions
297	45.5.3.12 DTE XS options 45.5.3.13 DTE XS management functions
299	45.5.3.14 Vendor specific MMD 1 management functions 45.5.3.15 Vendor specific MMD 2 management functions
300	45.5.3.16 Management frame structure
301	45.5.3.17 TC management functions
302	45.5.3.18 Clause 22 extension options
303	45.5.3.19 Clause 22 extension management functions 45.5.3.20 Signal timing characteristics
304	45.5.3.21 Electrical characteristics
305	46. Reconciliation Sublayer (RS) and 10 Gigabit Media Independent Interface (XGMII) 46.1 Overview
306	46.1.1 Summary of major concepts 46.1.2 Application 46.1.3 Rate of operation
307	46.1.4 Delay constraints 46.1.5 Allocation of functions 46.1.6 XGMII structure
308	46.1.7 Mapping of XGMII signals to PLS service primitives 46.1.7.1 Mapping of PLS_DATA.request 46.1.7.1.1 Function 46.1.7.1.2 Semantics of the service primitive
309	46.1.7.1.3 When generated 46.1.7.1.4 Effect of receipt 46.1.7.2 Mapping of PLS_DATA.indication 46.1.7.2.1 Function 46.1.7.2.2 Semantics of the service primitive 46.1.7.2.3 When generated 46.1.7.2.4 Effect of receipt
310	46.1.7.3 Mapping of PLS_CARRIER.indication 46.1.7.4 Mapping of PLS_SIGNAL.indication 46.1.7.5 Mapping of PLS_DATA_VALID.indication 46.1.7.5.1 Function 46.1.7.5.2 Semantics of the service primitive 46.1.7.5.3 When generated 46.1.7.5.4 Effect of receipt
311	46.2 XGMII data stream 46.2.1 Inter-frame 46.2.2 Preamble and start of frame delimiter
312	46.2.3 Data 46.2.4 End of frame delimiter 46.2.5 Definition of Start of Packet and End of Packet Delimiters 46.3 XGMII functional specifications
313	46.3.1 Transmit 46.3.1.1 TX_CLK (10 Gb/s transmit clock) 46.3.1.2 TXC (transmit control) 46.3.1.3 TXD (transmit data)
315	46.3.1.4 Start control character alignment
316	46.3.1.5 Transmit direction LPI transition
317	46.3.2 Receive 46.3.2.1 RX_CLK (receive clock) 46.3.2.2 RXC (receive control)
319	46.3.2.3 RXD (receive data) 46.3.2.4 Receive direction LPI transition
320	46.3.3 Error and fault handling 46.3.3.1 Response to error indications by the XGMII 46.3.3.2 Conditions for generation of transmit Error control characters 46.3.3.3 Response to received invalid frame sequences
321	46.3.4 Link fault signaling
322	46.3.4.1 Conventions 46.3.4.2 Variables and counters 46.3.4.3 State diagram
323	46.4 LPI assertion and detection
324	46.4.1 LPI messages 46.4.2 Transmit LPI state diagram
325	46.4.2.1 Variables and counters
326	46.4.3 Considerations for transmit system behavior 46.4.4 Considerations for receive system behavior 46.5 XGMII electrical characteristics
328	46.6 Protocol implementation conformance statement (PICS) proforma for Clause 46, Reconciliation Sublayer (RS) and 10 Gigabit Media Independent Interface (XGMII) 46.6.1 Introduction 46.6.2 Identification 46.6.2.1 Implementation identification 46.6.2.2 Protocol summary
329	46.6.2.3 Major capabilities/options 46.6.3 PICS proforma Tables for Reconciliation Sublayer and 10 Gigabit Media Independent Interface 46.6.3.1 General 46.6.3.2 Mapping of PLS service primitives
330	46.6.3.3 Data stream structure
331	46.6.3.4 LPI functions 46.6.3.5 Link Interruption 46.6.3.6 XGMII signal functional specifications
332	46.6.3.7 Link fault signaling state diagram
333	46.6.3.8 Electrical characteristics
334	47. XGMII Extender Sublayer (XGXS) and 10 Gigabit Attachment Unit Interface (XAUI) 47.1 Overview
335	47.1.1 Summary of major concepts 47.1.2 Application 47.1.3 Rate of operation
336	47.1.4 Allocation of functions 47.1.5 Global signal detect function 47.1.6 Global transmit disable function 47.2 Functional specifications 47.2.1 PCS and PMA functionality
337	47.2.2 Delay constraints 47.3 XAUI Electrical characteristics 47.3.1 Signal levels 47.3.2 Signal paths
338	47.3.3 Driver characteristics 47.3.3.1 Load 47.3.3.2 Amplitude and swing
339	47.3.3.3 Transition time 47.3.3.4 Output impedance 47.3.3.5 Driver template and jitter
340	47.3.4 Receiver characteristics 47.3.4.1 Bit error ratio 47.3.4.2 Reference input signals
341	47.3.4.3 Input signal amplitude 47.3.4.4 AC-coupling 47.3.4.5 Input impedance 47.3.4.6 Jitter tolerance
342	47.3.4.7 EEE receiver timing 47.3.5 Interconnect characteristics 47.3.5.1 Characteristic impedance 47.3.5.2 Connector impedance
343	47.4 Electrical measurement requirements 47.4.1 Compliance interconnect definition
344	47.4.2 Eye template measurements
345	47.4.3 Jitter test requirements 47.4.3.1 Transmit jitter 47.4.3.2 Jitter tolerance 47.5 Environmental specifications
346	47.6 Protocol implementation conformance statement (PICS) proforma for Clause 47, XGMII Extender (XGMII) and 10 Gigabit Attachment Unit Interface (XAUI) 47.6.1 Introduction 47.6.2 Identification 47.6.2.1 Implementation identification 47.6.2.2 Protocol summary
347	47.6.3 Major capabilities/options 47.6.4 PICS Proforma tables for XGXS and XAUI 47.6.4.1 Compatibility considerations 47.6.4.2 XGXS and XAUI functions 47.6.4.3 Electrical characteristics
348	47.6.4.4 LPI functions
349	48. Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) sublayer, type 10GBASE-X 48.1 Overview 48.1.1 Objectives
350	48.1.2 Relationship of 10GBASE-X to other standards 48.1.3 Summary of 10GBASE-X sublayers 48.1.3.1 Physical Coding Sublayer (PCS)
351	48.1.3.2 Physical Medium Attachment (PMA) sublayer 48.1.3.3 Physical Medium Dependent (PMD) sublayer 48.1.4 Rate of operation 48.1.5 Allocation of functions
352	48.1.6 Inter-sublayer interfaces 48.1.7 Functional block diagram
353	48.1.8 Special symbols 48.2 Physical Coding Sublayer (PCS) 48.2.1 PCS service interface (XGMII) 48.2.2 Functions within the PCS
354	48.2.3 Use of code-groups
356	48.2.4 Ordered sets and special code-groups 48.2.4.1 Data (/D/)
358	48.2.4.2 Idle (\|\|I\|\|) and Low Power Idle (\|\|LPIDLE\|\|)
359	48.2.4.2.1 Sync \|\|K\|\|
360	48.2.4.2.2 Align \|\|A\|\| 48.2.4.2.3 Skip \|\|R\|\|
361	48.2.4.3 Encapsulation 48.2.4.3.1 Start \|\|S\|\| 48.2.4.3.2 Terminate \|\|T\|\| 48.2.4.4 Error /E/ 48.2.4.5 Link status
362	48.2.4.5.1 Sequence \|\|Q\|\| 48.2.5 Management function requirements
363	48.2.6 Detailed functions and state diagrams 48.2.6.1 State variables 48.2.6.1.1 Notation conventions
364	48.2.6.1.2 Constants
365	48.2.6.1.3 Variables
368	48.2.6.1.4 Functions
369	48.2.6.1.5 Counters 48.2.6.1.6 Timers
370	48.2.6.1.7 Messages
371	48.2.6.2 State diagrams 48.2.6.2.1 Transmit 48.2.6.2.2 Synchronization
373	48.2.6.2.3 Deskew 48.2.6.2.4 Receive 48.2.6.2.5 LPI state diagrams
379	48.2.6.2.6 LPI status and management
380	48.2.6.3 Initialization process 48.2.6.4 Link status reporting 48.2.6.4.1 Link status detection 48.2.6.4.2 Link status signaling 48.2.6.4.3 Link status messages 48.2.7 Auto-Negotiation for Backplane Ethernet 48.3 Physical Medium Attachment (PMA) sublayer
381	48.3.1 Functions within the PMA 48.3.1.1 PMA transmit process 48.3.1.2 PMA receive process
382	48.3.2 Service interface 48.3.2.1 PMA_UNITDATA.request 48.3.2.1.1 Semantics of the service primitive 48.3.2.1.2 When generated 48.3.2.1.3 Effect of receipt 48.3.2.2 PMA_UNITDATA.indication 48.3.2.2.1 Semantics of the service primitive 48.3.2.2.2 When generated 48.3.2.2.3 Effect of receipt
383	48.3.3 Loopback mode 48.3.3.1 Receiver considerations 48.3.3.2 Transmitter considerations 48.3.4 Test functions 48.4 Compatibility considerations 48.5 Delay constraints
384	48.6 Environmental specifications
385	48.7 Protocol implementation conformance statement (PICS) proforma for Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) sublayer, type 10GBASE-X 48.7.1 Introduction 48.7.2 Identification 48.7.2.1 Implementation identification 48.7.2.2 Protocol summary
386	48.7.3 Major capabilities/options 48.7.4 PICS proforma tables for the PCS and PMA sublayer, type 10GBASE-X 48.7.4.1 Compatibility considerations 48.7.4.2 PCS functions
388	48.7.4.3 PMA Functions 48.7.4.4 Interface functions 48.7.4.5 LPI functions
389	49. Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R 49.1 Overview 49.1.1 Scope 49.1.2 Objectives 49.1.3 Relationship of 10GBASE-R to other standards
390	49.1.4 Summary of 10GBASE-R and 10GBASE-W sublayers 49.1.4.1 Physical Coding Sublayer (PCS)
391	49.1.4.2 WAN Interface Sublayer (WIS) 49.1.4.3 Physical Medium Attachment (PMA) sublayer 49.1.4.4 Physical Medium Dependent (PMD) sublayer 49.1.4.5 Bit ordering across 10GBASE-R and 10GBASE-W sublayers.
392	49.1.5 Inter-sublayer interfaces
393	49.1.6 Functional block diagram
394	49.2 Physical Coding Sublayer (PCS) 49.2.1 PCS service interface (XGMII) 49.2.2 Functions within the PCS
395	49.2.3 Use of blocks 49.2.4 64B/66B transmission code 49.2.4.1 Notation conventions
396	49.2.4.2 Transmission order 49.2.4.3 Block structure
398	49.2.4.4 Control codes 49.2.4.5 Ordered sets
399	49.2.4.6 Valid and invalid blocks 49.2.4.7 Idle (/I/) and Low Power Idle (/LI/)
400	49.2.4.8 Start (/S/) 49.2.4.9 Terminate (/T/) 49.2.4.10 ordered set (/O/) 49.2.4.11 Error (/E/)
401	49.2.5 Transmit process 49.2.6 Scrambler
402	49.2.7 Gearbox 49.2.8 Test-pattern generators
403	49.2.9 Block synchronization 49.2.10 Descrambler 49.2.11 Receive process
404	49.2.12 Test-pattern checker
405	49.2.13 Detailed functions and state diagrams 49.2.13.1 State diagram conventions 49.2.13.2 State variables 49.2.13.2.1 Constants 49.2.13.2.2 Variables
407	49.2.13.2.3 Functions
408	49.2.13.2.4 Counters
409	49.2.13.2.5 Timers
410	49.2.13.3 State diagrams 49.2.13.3.1 LPI state diagrams
413	49.2.14 PCS Management 49.2.14.1 Status
414	49.2.14.2 Counters 49.2.14.3 Test mode control 49.2.14.4 Loopback 49.2.15 Delay constraints
415	49.2.16 Auto-Negotiation for Backplane Ethernet
419	49.3 Protocol implementation conformance statement (PICS) proforma for Clause 49, Physical Coding Sublayer (PCS) type 10GBASE-R 49.3.1 Introduction 49.3.2 Identification 49.3.2.1 Implementation identification 49.3.2.2 Protocol summary
420	49.3.3 Major capabilities/options 49.3.4 PICS Proforma Tables for PCS, type 10GBASE-R 49.3.4.1 Coding rules
421	49.3.4.2 Scrambler and Descrambler 49.3.5 Test-pattern modes
422	49.3.5.1 Bit order 49.3.6 Management 49.3.6.1 State diagrams 49.3.6.2 WIS
423	49.3.6.3 Loopback 49.3.6.4 Delay Constraints 49.3.6.5 Auto-Negotiation for Backplane Ethernet functions
424	49.3.6.6 LPI functions
425	50. WAN Interface Sublayer (WIS), type 10GBASE-W 50.1 Overview 50.1.1 Scope
426	50.1.2 Objectives
427	50.1.3 Relationship to other sublayers 50.1.4 Summary of functions
428	50.1.5 Sublayer interfaces 50.1.6 Functional block diagram 50.1.7 Notational conventions
429	50.2 WIS Service Interface 50.2.1 WIS_UNITDATA.request 50.2.1.1 Semantics of the service primitive 50.2.1.2 When generated
430	50.2.1.3 Effect of receipt 50.2.2 WIS_UNITDATA.indication 50.2.2.1 Semantics of the service primitive 50.2.2.2 When generated 50.2.2.3 Effect of receipt 50.2.3 WIS_SIGNAL.request 50.2.3.1 Semantics of the service primitive
431	50.2.3.2 When generated 50.2.3.3 Effect of receipt 50.2.4 WIS_SIGNAL.indication 50.2.4.1 Semantics of the service primitive 50.2.4.2 When generated 50.2.4.3 Effect of receipt 50.3 Functions within the WIS
433	50.3.1 Payload mapping and data-unit delineation
434	50.3.1.1 Transmit payload mapping
435	50.3.1.2 Receive payload mapping 50.3.2 WIS frame generation
436	50.3.2.1 Transmit Path Overhead insertion
437	50.3.2.2 Transmit Line Overhead insertion
438	50.3.2.3 Transmit Section Overhead insertion
439	50.3.2.4 Receive Path, Line, and Section Overhead extraction
440	50.3.2.5 Fault processing
441	50.3.3 Scrambling
442	50.3.3.1 Scrambler polynomial 50.3.3.2 Scrambler bit ordering 50.3.4 Octet and frame delineation 50.3.5 Error propagation
443	50.3.5.1 Propagated errors 50.3.5.2 Error propagation timing 50.3.5.3 Loss of Code-group Delineation 50.3.6 Mapping between WIS and PMA
444	50.3.7 WIS data delay constraints
445	50.3.8 WIS test-pattern generator and checker 50.3.8.1 Square wave test pattern 50.3.8.2 PRBS31 test pattern
446	50.3.8.3 Mixed-frequency test pattern
447	50.3.8.3.1 Test Signal Structure (TSS)
448	50.3.8.3.2 Continuous Identical Digits 50.3.9 Loopback 50.3.10 Link status 50.3.11 Management interface
449	50.3.11.1 Management registers 50.3.11.2 WIS managed object class 50.3.11.3 Management support objects
450	50.4 Synchronization state diagram 50.4.1 State diagram variables 50.4.1.1 Constants
451	50.4.1.2 Variables 50.4.1.3 Functions
452	50.4.1.4 Counters 50.4.2 State diagram
454	50.4.3 Parameter values 50.5 Environmental specifications
456	50.6 Protocol implementation conformance statement (PICS) proforma for Clause 50, WAN Interface Sublayer (WIS), type 10GBASE-W 50.6.1 Introduction 50.6.2 Identification 50.6.2.1 Implementation identification 50.6.2.2 Protocol summary
457	50.6.3 Major capabilities/options 50.6.4 PICS proforma tables for the WAN Interface Sublayer (WIS), type 10GBASE-W 50.6.4.1 Compatibility considerations 50.6.4.2 WIS transmit functions
458	50.6.4.3 WIS receive functions
459	50.6.4.4 State diagrams
460	50.6.4.5 Error notification 50.6.4.6 Management registers and functions
461	50.6.4.7 WIS test-pattern generator and checker
462	51. Physical Medium Attachment (PMA) sublayer, type Serial 51.1 Overview 51.1.1 Scope 51.1.2 Summary of functions
463	51.2 PMA Service Interface 51.2.1 PMA_UNITDATA.request 51.2.1.1 Semantics of the service primitive 51.2.1.2 When generated
464	51.2.1.3 Effect of receipt 51.2.2 PMA_UNITDATA.indication 51.2.2.1 Semantics of the service primitive 51.2.2.2 When generated 51.2.2.3 Effect of receipt 51.2.3 PMA_SIGNAL.indication 51.2.3.1 Semantics of the service primitive 51.2.3.2 When generated 51.2.3.3 Effect of receipt
465	51.2.4 PMA_RXMODE.request 51.2.4.1 Semantics of the service primitive 51.2.4.2 When generated 51.2.4.3 Effect of receipt 51.2.5 PMA_TXMODE.request 51.2.5.1 Semantics of the service primitive 51.2.5.2 When generated 51.2.5.3 Effect of receipt 51.2.6 PMA_ENERGY.indication 51.2.6.1 Semantics of the service primitive
466	51.2.6.2 When generated 51.2.6.3 Effect of receipt 51.3 Functions within the PMA 51.3.1 PMA transmit function 51.3.2 PMA receive function 51.3.3 Delay Constraints
467	51.4 Sixteen-Bit Interface (XSBI)
468	51.4.1 Required signals
470	51.4.2 Optional Signals
471	51.5 General electrical characteristics of the XSBI 51.5.1 DC characteristics 51.5.2 Valid signal levels
472	51.5.3 Rise and fall time definition 51.5.4 Output load 51.6 XSBI transmit interface electrical characteristics 51.6.1 XSBI transmit interface timing
473	51.6.1.1 PMA client output timing
474	51.6.1.2 PMA input timing 51.6.2 XSBI PMA_TX_CLK and PMA_TXCLK_SRC Specification
475	51.7 XSBI receive interface electrical characteristics 51.7.1 XSBI receive interface timing
476	51.7.1.1 PMA output timing
477	51.7.1.2 PMA client input timing 51.7.2 XSBI PMA_RX_CLK specification 51.8 PMA loopback mode (optional)
478	51.9 Environmental specifications
479	51.10 Protocol implementation conformance statement (PICS) proforma for Clause 51, Physical Medium Attachment (PMA) sublayer, type Serial 51.10.1 Introduction 51.10.2 Identification 51.10.2.1 Implementation identification 51.10.2.2 Protocol summary
480	51.10.3 Major capabilities/options 51.10.4 PICS proforma tables for the PMA Interface Sublayer, type Serial 51.10.4.1 Compatibility considerations 51.10.4.2 PMA transmit functions
481	51.10.4.3 PMA receive functions 51.10.4.4 PMA delay constraints
482	52. Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-S (short wavelength serial), 10GBASE-L (long wavelength serial), and 10GBASE-E (extra long wavelength serial) 52.1 Overview
483	52.1.1 Physical Medium Dependent (PMD) sublayer service interface 52.1.1.1 PMD_UNITDATA.request
484	52.1.1.1.1 Semantics of the service primitive 52.1.1.1.2 When generated 52.1.1.1.3 Effect of receipt 52.1.1.2 PMD_UNITDATA.indication 52.1.1.2.1 Semantics of the service primitive 52.1.1.2.2 When generated 52.1.1.2.3 Effect of receipt 52.1.1.3 PMD_SIGNAL.indication 52.1.1.3.1 Semantics of the service primitive
485	52.1.1.3.2 When generated 52.1.1.3.3 Effect of receipt 52.2 Delay constraints 52.3 PMD MDIO function mapping
486	52.4 PMD functional specifications 52.4.1 PMD block diagram 52.4.2 PMD Transmit function 52.4.3 PMD Receive function 52.4.4 PMD Signal Detect function
487	52.4.5 PMD_reset function 52.4.6 PMD_fault function 52.4.7 PMD_global_transmit_disable function
488	52.4.8 PMD_transmit_fault function 52.4.9 PMD_receive_fault function 52.5 PMD to MDI optical specifications for 10GBASE-S
489	52.5.1 10GBASE-S transmitter optical specifications
491	52.5.2 10GBASE-S receive optical specifications 52.5.3 10GBASE-S link power budgets (informative) 52.6 PMD to MDI optical specifications for 10GBASE-L
492	52.6.1 10GBASE-L transmitter optical specifications
494	52.6.2 10GBASE-L receive optical specifications 52.6.3 10GBASE-L link power budgets (informative)
495	52.7 PMD to MDI optical specifications for 10GBASE-E
496	52.7.1 10GBASE-E transmitter optical specifications
497	52.7.2 10GBASE-E receive optical specifications 52.7.3 10GBASE-E link power budgets (informative) 52.8 Jitter specifications for 10GBASE-R and 10GBASE-W
498	52.8.1 Sinusoidal jitter for receiver conformance test
499	52.9 Optical measurement requirements 52.9.1 Test patterns 52.9.1.1 Test-pattern definition
501	52.9.1.2 Square wave pattern definition 52.9.2 Center wavelength and spectral width measurements 52.9.3 Average optical power measurements 52.9.4 Extinction ratio measurements 52.9.5 Optical modulation amplitude (OMA) test procedure
502	52.9.6 Relative intensity noise optical modulation amplitude (RINxOMA) measuring procedure 52.9.6.1 General test description 52.9.6.2 Component descriptions
503	52.9.6.3 Test Procedure
504	52.9.7 Transmitter optical waveform
505	52.9.8 Receiver sensitivity measurements
506	52.9.9 Stressed receiver conformance test 52.9.9.1 Stressed receiver conformance test block diagram
508	52.9.9.2 Parameter definitions
509	52.9.9.3 Stressed receiver conformance test signal characteristics and calibration
510	52.9.9.4 Stressed receiver conformance test procedure
511	52.9.10 Transmitter and dispersion penalty measurement 52.9.10.1 Reference transmitter requirements 52.9.10.2 Channel requirements
512	52.9.10.3 Reference receiver requirements 52.9.10.4 Test procedure
513	52.9.11 Measurement of the receiver 3 dB electrical upper cutoff frequency
514	52.10 Environmental specifications 52.10.1 General safety 52.10.2 Laser safety 52.10.3 Installation 52.11 Environment 52.11.1 Electromagnetic emission
515	52.11.2 Temperature, humidity, and handling 52.12 PMD labeling requirements 52.13 Fiber optic cabling model
516	52.14 Characteristics of the fiber optic cabling (channel) 52.14.1 Optical fiber and cable 52.14.2 Optical fiber connection 52.14.2.1 Connection insertion loss
517	52.14.2.2 Maximum discrete reflectance 52.14.3 10GBASE-E attenuator management
518	52.14.4 Medium Dependent Interface (MDI) requirements
519	52.15 Protocol implementation conformance statement (PICS) proforma for Clause 52, Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-S (short wavelength serial), 10GBASE-L (long wavelength serial), and 10GBASE-E (extra long w… 52.15.1 Introduction 52.15.2 Identification 52.15.2.1 Implementation identification 52.15.2.2 Protocol summary
520	52.15.2.3 Major capabilities/options
521	52.15.3 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, types 10GBASE-R and 10GBASE-W 52.15.3.1 PMD functional specifications 52.15.3.2 Management functions
522	52.15.3.3 PMD to MDI optical specifications for 10GBASE-SR 52.15.3.4 PMD to MDI optical specifications for 10GBASE-SW 52.15.3.5 PMD to MDI optical specifications for 10GBASE-LR
523	52.15.3.6 PMD to MDI optical specifications for 10GBASE-LW 52.15.3.7 PMD to MDI optical specifications for 10GBASE-ER 52.15.3.8 PMD to MDI optical specifications for 10GBASE-EW
524	52.15.3.9 Optical measurement requirements 52.15.3.10 Characteristics of the fiber optic cabling and MDI
525	52.15.3.11 Environmental specifications 52.15.3.12 Environment
526	53. Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-LX4 53.1 Overview 53.1.1 Physical Medium Dependent (PMD) service interface 53.1.2 PMD_UNITDATA.request
527	53.1.2.1 Semantics of the service primitive 53.1.2.2 When generated 53.1.2.3 Effect of Receipt 53.1.3 PMD_UNITDATA.indication 53.1.3.1 Semantics of the service primitive
528	53.1.3.2 When generated 53.1.3.3 Effect of receipt 53.1.4 PMD_SIGNAL.indication 53.1.4.1 Semantics of the service primitive 53.1.4.2 When generated 53.1.4.3 Effect of receipt 53.2 Delay constraints 53.3 PMD MDIO function mapping
529	53.4 PMD functional specifications 53.4.1 PMD block diagram
530	53.4.2 PMD transmit function
531	53.4.3 PMD receive function 53.4.4 Global PMD signal detect function 53.4.5 PMD lane by lane signal detect function
532	53.4.6 PMD reset function 53.4.7 Global PMD transmit disable function 53.4.8 PMD lane by lane transmit disable function 53.4.9 PMD fault function 53.4.10 PMD transmit fault function (optional) 53.4.11 PMD receive fault function (optional) 53.5 Wavelength-division multiplexed-lane assignments 53.6 Operating ranges for 10GBASE-LX4 PMD
534	53.7 PMD to MDI optical specifications for 10GBASE-LX4 53.7.1 Transmitter optical specifications
535	53.7.2 Receive optical specifications 53.7.3 Worst case 10GBASE-LX4 link power budget and penalties (informative) 53.8 Jitter specifications for each lane of the 10GBASE-LX4 PMD 53.8.1 Transmit jitter specification
537	53.8.1.1 Channel requirements for transmit jitter testing 53.8.1.2 Test pattern requirements for transmit jitter testing 53.8.2 Receive jitter tolerance specification 53.8.2.1 Input jitter for receiver jitter test
538	53.8.2.2 Added sinusoidal jitter for receiver jitter test
539	53.9 Optical measurement requirements 53.9.1 Wavelength range measurements
540	53.9.2 Optical power measurements 53.9.3 Source spectral window measurements 53.9.4 Extinction ratio measurements 53.9.5 Optical Modulation Amplitude (OMA) measurements 53.9.6 Relative Intensity Noise [RIN12(OMA)] 53.9.7 Transmitter optical waveform (transmit eye)
542	53.9.8 Transmit rise/fall characteristics 53.9.9 Receive sensitivity measurements 53.9.10 Transmitter jitter conformance (per lane) 53.9.10.1 Block diagram and general description of test set up
543	53.9.10.2 Channel requirements for transmit jitter testing
544	53.9.10.3 Transmit jitter test procedure 53.9.11 Receive sensitivity measurements 53.9.12 Stressed receiver conformance test 53.9.12.1 Block diagram of stressed receiver tolerance test set up
545	53.9.12.2 Stressed receiver conformance test procedure 53.9.12.3 Characterization of receiver input signal
546	53.9.12.4 Jitter tolerance test procedure 53.9.13 Measurement of the receiver 3 dB electrical upper cutoff frequency
547	53.9.14 Conformance test signal at TP3 for receiver testing
549	53.9.15 Receiver test suite for WDM conformance testing
551	53.10 Environmental specifications 53.10.1 General safety 53.10.2 Laser safety
552	53.10.3 Installation 53.11 Environment 53.11.1 Electromagnetic emission 53.11.2 Temperature, humidity, and handling 53.12 PMD labeling requirements
553	53.13 Fiber optic cabling model 53.14 Characteristics of the fiber optic cabling (channel) 53.14.1 Optical fiber and cable
554	53.14.2 Optical fiber connection 53.14.2.1 Connection insertion loss
555	53.14.2.2 Connection return loss 53.14.3 Medium Dependent Interface (MDI)
556	53.15 Protocol implementation conformance statement (PICS) proforma for Clause 53, Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-LX4 53.15.1 Introduction 53.15.2 Identification 53.15.2.1 Implementation identification 53.15.2.2 Protocol summary
557	53.15.3 Major capabilities/options
558	53.15.4 PICS proforma tables for 10GBASE-LX4 and baseband medium 53.15.4.1 PMD Functional specifications
559	53.15.4.2 PMD to MDI optical specifications for 10GBASE-LX4 53.15.4.3 Management functions
560	53.15.4.4 Jitter specifications
561	53.15.4.5 Optical measurement requirements
564	53.15.4.6 Characteristics of the fiber optic cabling
565	54. Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-CX4 54.1 Overview
566	54.2 Physical Medium Dependent (PMD) service interface 54.3 Delay constraints 54.4 PMD MDIO function mapping 54.5 PMD functional specifications 54.5.1 Link block diagram
567	54.5.2 PMD Transmit function 54.5.3 PMD Receive function 54.5.4 Global PMD signal detect function
568	54.5.5 PMD lane-by-lane signal detect function 54.5.6 Global PMD transmit disable function 54.5.7 PMD lane-by-lane transmit disable function
569	54.5.8 Loopback mode 54.5.9 PMD fault function 54.5.10 PMD transmit fault function 54.5.11 PMD receive fault function 54.6 MDI Electrical specifications for 10GBASE-CX4 54.6.1 Signal levels
570	54.6.2 Signal paths 54.6.3 Transmitter characteristics
571	54.6.3.1 Test fixtures 54.6.3.2 Test-fixture impedance 54.6.3.3 Signaling speed range
572	54.6.3.4 Output amplitude
573	54.6.3.5 Output return loss
574	54.6.3.6 Differential output template
575	54.6.3.7 Transition time 54.6.3.8 Transmit jitter 54.6.3.9 Transmit jitter test requirements
576	54.6.4 Receiver characteristics 54.6.4.1 Bit error ratio 54.6.4.2 Signaling speed range 54.6.4.3 AC-coupling 54.6.4.4 Input signal amplitude
577	54.6.4.5 Input return loss 54.7 Cable assembly characteristics
578	54.7.1 Characteristic impedance and reference impedance 54.7.2 Cable assembly insertion loss
579	54.7.3 Cable assembly return loss 54.7.4 Near-End Crosstalk (NEXT) 54.7.4.1 Differential Near-End Crosstalk
580	54.7.4.2 Multiple Disturber Near-End Crosstalk (MDNEXT)
581	54.7.5 Far-End Crosstalk (FEXT) 54.7.5.1 Equal Level Far-End Crosstalk (ELFEXT) loss 54.7.5.2 Multiple Disturber Equal Level Far-End Crosstalk (MDELFEXT) loss
582	54.7.6 Shielding 54.7.7 Crossover function
583	54.8 MDI specification 54.8.1 MDI connectors
584	54.8.2 Connector pin assignments 54.9 Environmental specifications
585	54.10 Protocol implementation conformance statement (PICS) proforma for Clause 54, Physical Medium Dependent (PMD) sublayer and baseband medium, type 10GBASE-CX4 54.10.1 Introduction 54.10.2 Identification 54.10.2.1 Implementation identification 54.10.2.2 Protocol summary
586	54.10.3 PICS proforma tables for 10GBASE-CX4 and baseband medium 54.10.4 Major capabilities/options
587	54.10.4.1 PMD Functional specifications
588	54.10.4.2 Management functions
589	54.10.4.3 Transmitter specifications
590	54.10.4.4 Receiver specifications 54.10.4.5 Cable assembly specifications
591	54.10.4.6 MDI connector specifications
592	55. Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer and baseband medium, type 10GBASE-T 55.1 Overview 55.1.1 Objectives
593	55.1.2 Relationship of 10GBASE-T to other standards 55.1.3 Operation of 10GBASE-T
597	55.1.3.1 Physical Coding Sublayer (PCS) 55.1.3.2 Physical Medium Attachment (PMA) sublayer
598	55.1.3.3 EEE capability
599	55.1.4 Signaling 55.1.5 Interfaces
600	55.1.6 Conventions in this clause 55.2 10GBASE-T service primitives and interfaces 55.2.1 Technology Dependent Interface 55.2.1.1 PMA_LINK.request 55.2.1.1.1 Semantics of the primitive
601	55.2.1.1.2 When generated 55.2.1.1.3 Effect of receipt 55.2.1.2 PMA_LINK.indication 55.2.1.2.1 Semantics of the primitive 55.2.1.2.2 When generated 55.2.1.2.3 Effect of receipt 55.2.2 PMA service interface
603	55.2.2.1 PMA_TXMODE.indication 55.2.2.1.1 Semantics of the primitive
604	55.2.2.1.2 When generated 55.2.2.1.3 Effect of receipt 55.2.2.2 PMA_CONFIG.indication 55.2.2.2.1 Semantics of the primitive 55.2.2.2.2 When generated 55.2.2.2.3 Effect of receipt 55.2.2.3 PMA_UNITDATA.request
605	55.2.2.3.1 Semantics of the primitive 55.2.2.3.2 When generated 55.2.2.3.3 Effect of receipt 55.2.2.4 PMA_UNITDATA.indication 55.2.2.4.1 Semantics of the primitive
606	55.2.2.4.2 When generated 55.2.2.4.3 Effect of receipt 55.2.2.5 PMA_SCRSTATUS.request 55.2.2.5.1 Semantics of the primitive 55.2.2.5.2 When generated 55.2.2.5.3 Effect of receipt 55.2.2.6 PMA_PCSSTATUS.request 55.2.2.6.1 Semantics of the primitive 55.2.2.6.2 When generated
607	55.2.2.6.3 Effect of receipt 55.2.2.7 PMA_RXSTATUS.indication 55.2.2.7.1 Semantics of the primitive 55.2.2.7.2 When generated 55.2.2.7.3 Effect of receipt 55.2.2.8 PMA_REMRXSTATUS.request 55.2.2.8.1 Semantics of the primitive 55.2.2.8.2 When generated
608	55.2.2.8.3 Effect of receipt 55.2.2.9 PMA_ALERTDETECT.indication 55.2.2.9.1 Semantics of the primitive 55.2.2.9.2 When generated 55.2.2.9.3 Effect of receipt 55.2.2.10 PCS_RX_LPI_STATUS.request 55.2.2.10.1 Semantics of the primitive 55.2.2.10.2 When generated 55.2.2.10.3 Effect of receipt
609	55.2.2.11 PMA_PCSDATAMODE.indication 55.2.2.11.1 Semantics of the primitive 55.2.2.11.2 When generated 55.2.2.11.3 Effect of receipt 55.2.2.12 PMA_FR_ACTIVE.indication 55.2.2.12.1 Semantics of the primitive 55.2.2.12.2 When generated 55.2.2.12.3 Effect of receipt 55.3 Physical Coding Sublayer (PCS) 55.3.1 PCS service interface (XGMII) 55.3.2 PCS functions
610	55.3.2.1 PCS Reset function
611	55.3.2.2 PCS Transmit function
612	55.3.2.2.1 Use of blocks 55.3.2.2.2 65B-LDPC transmission code 55.3.2.2.3 Notation conventions 55.3.2.2.4 Transmission order 55.3.2.2.5 Block structure
616	55.3.2.2.6 Control codes 55.3.2.2.7 Ordered sets
617	55.3.2.2.8 Valid and invalid blocks 55.3.2.2.9 Idle (/I/)
618	55.3.2.2.10 LPI (/LI/)
619	55.3.2.2.11 Start (/S/) 55.3.2.2.12 Terminate (/T/) 55.3.2.2.13 ordered set (/O/) 55.3.2.2.14 Error (/E/) 55.3.2.2.15 Transmit process
620	55.3.2.2.16 PCS scrambler
621	55.3.2.2.17 CRC8 55.3.2.2.18 LDPC encoder 55.3.2.2.19 DSQ128 bit mapping
622	55.3.2.2.20 DSQ128 to 4D-PAM16
623	55.3.2.2.21 65B-LDPC framer 55.3.2.2.22 EEE capability
624	55.3.2.3 PCS Receive function
625	55.3.2.3.1 Frame and block synchronization 55.3.2.3.2 PCS descrambler 55.3.2.3.3 CRC8 receive function 55.3.3 Test-pattern generators
626	55.3.4 PMA training side-stream scrambler polynomials
627	55.3.4.1 Generation of bits San, Sbn, Scn, Sdn 55.3.4.2 Generation of 4D symbols TAn, TBn, TCn, TDn
628	55.3.4.3 PMA training mode descrambler polynomials 55.3.5 LPI signaling
629	55.3.5.1 LPI Synchronization
630	55.3.5.2 Quiet period signaling 55.3.5.3 Refresh period signaling
631	55.3.6 Detailed functions and state diagrams 55.3.6.1 State diagram conventions 55.3.6.2 State diagram parameters 55.3.6.2.1 Constants 55.3.6.2.2 Variables
633	55.3.6.2.3 Timers
634	55.3.6.2.4 Functions
636	55.3.6.2.5 Counters 55.3.6.3 Messages 55.3.6.4 State diagrams
637	55.3.7 PCS management 55.3.7.1 Status 55.3.7.2 Counters
644	55.3.7.3 Loopback 55.4 Physical Medium Attachment (PMA) sublayer 55.4.1 PMA functional specifications
645	55.4.2 PMA functions 55.4.2.1 PMA Reset function 55.4.2.2 PMA Transmit function
646	55.4.2.2.1 Alert signal
647	55.4.2.2.2 Link failure signal 55.4.2.3 PMA transmit disable function 55.4.2.3.1 Global PMA transmit disable function 55.4.2.3.2 PMA pair by pair transmit disable function 55.4.2.3.3 PMA MDIO function mapping
648	55.4.2.4 PMA Receive function
649	55.4.2.5 PHY Control function
650	55.4.2.5.1 Infofield notation 55.4.2.5.2 Start of Frame Delimiter 55.4.2.5.3 Current transmitter settings
651	55.4.2.5.4 Next transmitter settings 55.4.2.5.5 Requested transmitter settings 55.4.2.5.6 Message Field
652	55.4.2.5.7 SNR_margin
653	55.4.2.5.8 Transition counter 55.4.2.5.9 Coefficient exchange handshake 55.4.2.5.10 Reserved Fields 55.4.2.5.11 Vendor-specific field 55.4.2.5.12 Coefficient Field 55.4.2.5.13 CRC16
654	55.4.2.5.14 Startup sequence
657	55.4.2.5.15 Fast retrain function 55.4.2.6 Link Monitor function
658	55.4.2.7 Refresh Monitor function 55.4.2.8 Clock Recovery function 55.4.3 MDI 55.4.3.1 MDI signals transmitted by the PHY
659	55.4.3.2 Signals received at the MDI 55.4.4 Automatic MDI/MDI-X configuration
660	55.4.5 State variables 55.4.5.1 State diagram variables
663	55.4.5.2 Timers
664	55.4.5.3 Functions 55.4.5.4 Counters
665	55.4.6 State diagrams 55.4.6.1 PHY Control state diagram
666	55.4.6.2 Transition counter state diagrams
668	55.4.6.3 Link Monitor state diagram
669	55.4.6.4 EEE Refresh monitor state diagram
670	55.4.6.5 Fast retrain state diagram 55.5 PMA electrical specifications 55.5.1 Isolation requirement
671	55.5.2 Test modes
673	55.5.2.1 Test fixtures
674	55.5.3 Transmitter electrical specifications 55.5.3.1 Maximum output droop 55.5.3.2 Transmitter linearity.
675	55.5.3.3 Transmitter timing jitter 55.5.3.4 Transmitter power spectral density (PSD) and power level
676	55.5.3.5 Transmit clock frequency 55.5.4 Receiver electrical specifications 55.5.4.1 Receiver differential input signals
677	55.5.4.2 Receiver frequency tolerance 55.5.4.3 Common-mode noise rejection 55.5.4.4 Alien crosstalk noise rejection
678	55.5.4.5 Short reach mode link test 55.5.4.5.1 Short reach test channels 55.6 Management interfaces 55.6.1 Support for Auto-Negotiation
679	55.6.1.1 10GBASE-T use of registers during Auto-Negotiation 55.6.1.2 10GBASE-T Auto-Negotiation page use
681	55.6.1.3 Sending Next Pages 55.6.2 MASTER-SLAVE configuration resolution
683	55.7 Link segment characteristics
684	55.7.1 Cabling system characteristics 55.7.2 Link segment transmission parameters 55.7.2.1 Insertion loss
685	55.7.2.2 Differential characteristic impedance 55.7.2.3 Return loss 55.7.2.4 Coupling parameters between duplex channels comprising one link segment 55.7.2.4.1 Differential near-end crosstalk
686	55.7.2.4.2 Multiple disturber near-end crosstalk (MDNEXT) loss 55.7.2.4.3 Multiple disturber power sum near-end crosstalk (PSNEXT) loss
687	55.7.2.4.4 Equal level far-end crosstalk (ELFEXT)
688	55.7.2.4.5 Multiple disturber equal level far-end crosstalk (MDELFEXT) 55.7.2.4.6 Multiple disturber power sum equal level far-end crosstalk (PS ELFEXT) 55.7.2.5 Maximum link delay 55.7.2.6 Link delay skew 55.7.3 Coupling parameters between link segments
689	55.7.3.1 Multiple disturber alien near-end crosstalk (MDANEXT) loss 55.7.3.1.1 Multiple disturber power sum alien near-end crosstalk (PSANEXT) loss
690	55.7.3.1.2 PSANEXT loss to insertion loss ratio requirements
692	55.7.3.2 Multiple disturber alien far-end crosstalk (MDAFEXT) loss 55.7.3.2.1 Multiple disturber power sum alien equal level far-end crosstalk (PSAELFEXT)
693	55.7.3.2.2 PSAELFEXT to insertion loss ratio requirements
695	55.7.3.3 Alien crosstalk margin computation
699	55.7.4 Noise environment
700	55.8 MDI specification 55.8.1 MDI connectors 55.8.2 MDI electrical specifications
701	55.8.2.1 MDI return loss 55.8.2.2 MDI impedance balance
702	55.8.2.3 MDI fault tolerance
703	55.9 Environmental specifications 55.9.1 General safety 55.9.2 Network safety 55.9.3 Installation and maintenance guidelines
704	55.9.4 Telephone voltages 55.9.5 Electromagnetic compatibility 55.9.6 Temperature and humidity 55.10 PHY labeling 55.11 Delay constraints
706	55.12 Protocol implementation conformance statement (PICS) proforma for Clause 55—Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer and baseband medium, type 10GBASE-T 55.12.1 Identification 55.12.1.1 Implementation identification 55.12.1.2 Protocol summary
707	55.12.2 Major capabilities/options 55.12.3 Physical Coding Sublayer (PCS)
709	55.12.3.1 PCS Receive functions 55.12.3.2 Other PCS functions 55.12.4 Physical Medium Attachment (PMA)
711	55.12.5 Management interface
712	55.12.6 PMA Electrical Specifications
713	55.12.7 Characteristics of the link segment
714	55.12.8 MDI requirements
715	55.12.9 General safety and environmental requirements 55.12.10 Timing requirements
716	Annex 44A (informative) Diagram of Data Flow 44A.1 10GBASE-R bit ordering 44A.2 10GBASE-W serial bit ordering 44A.3 10GBASE-LX4 bit ordering
722	44A.4 Loopback locations
723	Annex 45A (informative) Clause45 MDIO electrical interface 45A.1 MDIO driver 45A.2 Single Clause 45 electrical interface
724	45A.3 Clause 45 electrical interface for STA with Clause 22 electrical interface to PHYs 45A.4 Clause 22 electrical interface for STA with Clause 45 electrical interface to MMDs
726	Annex 48A (normative) Jitter test patterns 48A.1 High-frequency test pattern 48A.2 Low-frequency test pattern 48A.3 Mixed-frequency test pattern
727	48A.4 Continuous random test pattern (CRPAT)
728	48A.5 Continuous jitter test pattern (CJPAT)
729	48A.5.1 Continuous jitter test pattern (CJPAT) 10 bit values
733	Annex 48B (informative) Jitter test methods 48B.1 BER and jitter model 48B.1.1 Description of dual Dirac mathematical model
735	48B.1.2 Random Jitter 48B.1.3 Addition of Deterministic Jitter 48B.1.4 Effects of jitter high-pass filtering and CJPAT on deterministic jitter
736	48B.2 Jitter tolerance test methodologies 48B.2.1 Calibration of a signal source using the BERT scan technique
737	48B.3 Jitter output test methodologies 48B.3.1 Time domain measurement—Scope and BERT scan 48B.3.1.1 Jitter high pass filtering (using Golden PLL)
738	48B.3.1.2 Time domain scope measurement 48B.3.1.3 BERT Scan 48B.3.1.3.1 Approximate curve-fitting for BERT scan
739	48B.3.2 Time Interval Analysis 48B.3.2.1 TIA with Golden PLL
740	48B.3.2.1.1 Test method
741	48B.3.2.2 TIA with pattern trigger
742	48B.3.2.2.1 Test Method 48B.3.2.3 Approximate curve fitting for TIA bathtub curve
743	Annex 50A (informative) Thresholds for Severely Errored Second calculations 50A.1 Section SES threshold 50A.2 Line SES threshold 50A.3 Path SES threshold
744	50A.4 Definition of Path Block Error 50A.5 Definition of Far End Path Block Error
745	Annex 55A (normative) LDPC details 55A.1 The generator matrix 55A.2 The sparse parity check matrix H
746	Annex 55B (informative) Additional cabling design guidelines for 10GBASE-T 55B.1 Alien crosstalk considerations
747	55B.1.1 Alien crosstalk mitigation
748	55B.1.2 Alien crosstalk mitigation procedure

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Standard Title	IEEE Standard for Ethernet
Published Code	IEEE
Publication Date	2015

IEEE 802.3-2015

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